Analog front end for dtv, dtv system having the same, and operation methods thereof

A digital TV processing system comprising:

• a tuner which generates at least one of a single-ended sound intermediate frequency signal and differential TV broadcast signals from radio frequency signals;
• an analog front end (AFE) which selectively processes the generated single-ended sound intermediate frequency signal and the generated differential TV broadcast signals;
• and
• a demodulator which demodulates a digital code output from the AFE,
• wherein the AFE comprises:
• a first selection circuit which outputs differential sound intermediate frequency signals generated based on the generated single-ended sound intermediate frequency signal or the generated differential TV broadcast signals, in response to a first selection signal;
• a second selection circuit which outputs a clock signal among a plurality of clock signals having different sampling frequencies, in response to a second selection signal;
• and
• an analog-to-digital converter which converts the output signals output from the first selection circuit to the digital code, according to a sampling frequency of the output clock signal output from the second selection circuit.

A signal processing circuit comprising:

• an analog-to-digital converter which converts differential analog signals to a digital code, in response to a sampling clock signal;
• a fractional-N phase locked loop (PLL) which receives a clock signal as an input clock signal;
• and
• a first selector which selectively outputs one of the clock signal and an output clock signal output from the fractional-N PLL as the sampling clock signal, in response to a first selection signal.

A digital TV processing system comprising:

• an analog front end (AFE) which converts differential TV broadcast signals to a digital code according to a sampling clock signal;
• and
• a demodulator which demodulates the digital code,
• wherein the AFE comprises:
• an analog-to-digital converter which converts differential analog signals to the digital code, in response to the sampling clock signal;
• a fractional-N phase locked loop which receives a clock signal as an input clock signal;
• and
• a first selector which selectively outputs one of the clock signal and an output clock signal output from the fractional-N phase locked loop as the sampling clock signal, in response to a first selection signal.