Transmission channel for ultrasound applications
AssigneeSTMicroelectronics S.r.l.
InventorsSandro Rossi, Giulio Ricotti, Davide Ugo Ghisu, Antonio Ricciardo
Life of this patent
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Abstract
A transmission channel configured to transmit high-voltage pulses and to receive echoes of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.
Claims38
A transmission channel, comprising:
- a clamp including:
- a clamp output;
- a clamp input configured to couple to a reference voltage;
- a first clamping transistor;
- a second clamping transistor;
- a first switching off transistor coupled between the output and the first clamping transistor;
- and
- a second switching off transistor of the clamp coupled between the output and the second clamping transistor, wherein,
- the first and second clamping transistors are high-voltage MOS transistors of complementary types;
- the first clamping transistor is coupled between the first switching off transistor and the input, the first clamping transistor and the first switching off transistor having body diodes coupled together in anti-series;
- and
- the second clamping transistor is coupled between the second switching off transistor and the input, the second clamping transistor and the second switching off transistor having body diodes coupled together in anti-series;
- and
- a reset block including:
- a first memory diode coupled to a conduction terminal of the first clamp transistor and configured to couple to a conduction terminal of a first transistor of a high-voltage buffer;
- and
- a second memory diode coupled to a conduction terminal of the second clamp transistor and configured to couple to a conduction terminal of a second transistor of the high-voltage buffer.
A transmission channel, comprising:
- a clamp including:
- a clamp output;
- a clamp input configured to couple to a reference voltage;
- a first clamping transistor;
- a second clamping transistor;
- a first switching off transistor coupled between the output and the first clamping transistor;
- and
- a second switching off transistor of the clamp coupled between the output and the second clamping transistor, wherein,
- the first and second clamping transistors are high-voltage MOS transistors of complementary types;
- the first clamping transistor is coupled between the first switching off transistor and the input, the first clamping transistor and the first switching off transistor having body diodes coupled together in anti-series;
- and
- the second clamping transistor is coupled between the second switching off transistor and the input, the second clamping transistor and the second switching off transistor having body diodes coupled together in anti-series;
- and
- a switching circuit, including:
- a connection terminal;
- an output terminal;
- first and second voltage reference terminals;
- first and second switching transistors electrically coupled in series to each other, and having respective body diodes coupled in anti-series, between said connection terminal and said output terminal, the first switching transistor having a first control terminal and the second switching transistor having a second control terminal;
- and
- a bootstrap circuit connected to the first and second control terminals and to the first and second voltage references and including:
- first and second bootstrap nodes;
- a first parasitic capacitance electrically coupled between said first control terminal and the first bootstrap node;
- and
- a second parasitic capacitance electrically coupled between said second control terminal and the second bootstrap node, the first and second parasitic capacitances having capacitance values of at least one order of magnitude lower than gate-source capacitances of said first and second switching transistors.
A transmission channel, comprising:
- a voltage clamp including:
- a voltage clamp output;
- a first clamping transistor;
- and
- a second clamping transistor;
- a reset block including:
- a first memory diode coupled to a conduction terminal of the first clamp transistor and configured to couple to a conduction terminal of a first transistor of a high-voltage buffer;
- and
- a second memory diode coupled to a conduction terminal of the second clamp transistor and configured to couple to a conduction terminal of a second transistor of the high-voltage buffer;
- and
- a switching circuit, including:
- a connection terminal;
- an output terminal;
- first and second voltage reference terminals;
- first and second switching transistors electrically coupled in series to each other, and having respective body diodes coupled in anti-series, between said connection terminal and said output terminal, the first switching transistor having a first control terminal and the second switching transistor having a second control terminal;
- and
- a bootstrap circuit connected to the first and second control terminals and to the first and second voltage references and including:
- first and second bootstrap nodes;
- a first parasitic capacitance electrically coupled between said first control terminal and the first bootstrap node;
- and
- a second parasitic capacitance electrically coupled between said second control terminal and the second bootstrap node, the first and second parasitic capacitances having capacitance values of at least one order of magnitude lower than gate-source capacitances of said first and second switching transistors.
A system, comprising:
- means for generating high-voltage pulses;
- means for clamping a transmission channel output to a reference voltage;
- means for biasing the means for clamping between pulses;
- and
- means for receiving pulse echoes.
Dependencies are inferred from the claim text.