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US 2012/0268182 A1Published application
Clock gated circuit and digital system having the same
AssigneesSamsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate
InventorsHOIJIN LEE, Bai-Sun Kong
Life of this patent
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Abstract
A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.
Claims20
A clock gated circuit comprising:
- a pulse generator driven by a first power supply voltage and configured to receive a clock signal and to generate a pulse and an inverted pulse;
- and
- a pulse level shifter driven by a second power supply voltage higher than the first power supply voltage and configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.
A digital system comprising:
- a plurality of clock gated circuits configured to receive a clock signal having the amplitude of a first power supply voltage and to generate a pulse clock signal having the amplitude of a second power supply voltage, the first power supply voltage being lower than the second power supply voltage;
- and
- a plurality of flip-flops each connected with the clock gated circuits and configured to latch data in response to the pulse clock signal,
- wherein each of the clock gated circuits receive the clock signal, generates a pulse and an inverted pulse and generates the pulse clock signal in response to the pulse and the inverted pulse by converting a level of the pulse in response to an enable signal.
1 more element
A clock gated circuit comprising:
- a pulse generator configured to receive a clock signal to output first and second pulses, wherein the second pulse is the first pulse inverted and delayed, the amplitude of each pulse is a first voltage, and a high-level period of the second pulse is shorter than a half period of the clock signal;
- and
- a pulse level shifter configured to receive the first and second pulses to output a pulse clock signal having a second voltage higher than the first voltage level.
Dependencies are inferred from the claim text.