Semiconductor device
AssigneeElpida Memory, Inc.
InventorRyo FUJIMAKI
Life of this patent
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Abstract
A semiconductor device includes a DLL circuit, which comprises: a delay unit generating a second clock signal by delaying a first clock signal; a phase comparator circuit comparing the first clock signal and a signal generated by further delaying the second clock signal; a counter circuit outputting a count value that determines a delay amount of the delay unit to the delay unit, and up/down operating in response to the result of the phase comparison by the phase comparator circuit; and an initial delay amount control circuit detecting a cycle of the first clock signal at the time of initial setting operation, and outputting an initial value of the count value depending upon the detected cycle to the counter circuit.
Claims11
A semiconductor device comprising a DLL (Delay Locked Loop) circuit, wherein said DLL circuit comprises:
- a delay unit generating a second clock signal by delaying a first clock signal;
- a phase comparator circuit comparing said first clock signal and a signal generated by further delaying said second clock signal;
- a counter circuit outputting a count value that determines a delay amount of said delay unit to said delay unit, and up/down operating in response to the result of the phase comparison by said phase comparator circuit;
- and
- an initial delay amount control circuit detecting a cycle of said first clock signal at the time of initial setting operation, and outputting an initial value of said count value depending upon the detected cycle to said counter circuit.
The semiconductor device according to claim further comprising an output unit that outputs data to outside in response to a read command,
- wherein said second clock signal is a signal controlling an output timing of said output unit.
A semiconductor device comprising:
- a counter circuit storing code information;
- a delay control circuit receiving a first clock signal and producing a second clock signal, a difference in phase between the first and second clock signals being controlled by the code information;
- and
- an initial code control circuit receiving the first clock signal and controlling an initial value of the code information in response to a length of a clock cycle period of the first clock signal.
Dependencies are inferred from the claim text.