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US 2012/0268174 A1Published application
System for detecting a reset condition in an electronic circuit
AssigneeCerticom Corp.
InventorJay Scott FULLER
Life of this patent
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Abstract
There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.
Claims5
A system for generating a reset signal on a computing device, said system comprising:
- a plurality of circuit elements including:
- an input for receiving a reset signal of said computing device and,
- an output for outputting a string of data values, wherein said plurality of circuit elements output a predetermined pattern of data values when said reset signal is received and output an arbitrary pattern of data values upon power up of said computing device when said reset signal has not been received;
- a comparator including an input for receiving said string of data values, said comparator determining whether said string of data values matches said predetermined pattern of data values, wherein said comparator outputs a reset signal for said computing device when said string of data values fail to match said predetermined pattern of data values.
1 more element
Dependencies are inferred from the claim text.