Semiconductor device having gear down mode, method of controlling same, and information processing system

A method of controlling a semiconductor device, comprising:

• dividing a frequency of a first clock signal to generate a second clock signal;
• activating, in a first operation mode, a command generation circuit when both the second clock signal and a first chip select signal are activated;
• activating, in a second operation mode, the command generation circuit when the first chip select signal is activated regardless of the first and second clock signals;
• and
• generating a second command signal by supplying a first command signal to the command generation circuit that is activated.

An information processing system comprising:

• a first semiconductor device that outputs an external clock signal, an external chip select signal, and an external command signal;
• and
• a second semiconductor device comprising:
• a clock receiver that receives the external clock signal supplied from the first semiconductor device and outputs the first clock signal;
• a chip select receiver that receives the external chip select signal supplied from the first semiconductor device and outputs the first chip select signal;
• a command receiver that receives the external command signal supplied from the first semiconductor device and outputs the first command signal;
• a frequency division circuit that divides a frequency of the first clock signal to generate a second clock signal;
• a first logic circuit that receives the first chip select signal and the second clock signal to generate a second chip select signal;
• and
• a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on the first command signal.