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US 2012/0268166 A1Published application
Low-Current Logic Plus Driver Circuit
AssigneeEpcos AG
InventorsLéon C.M. van den Oever, Erwin Spits
Life of this patent
Estimating the term…
Abstract
A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.
Claims21
A circuit, comprising:
- a logic stage that includes a current limiter comprising a D-mode feedback transistor having a source, a drain, a gate and a gate-source junction, the current limiter further comprising a component that generates a voltage drop and a feedback loop connecting the source of the D-mode feedback transistor to the gate of the D-mode feedback transistor via the component that generates the voltage drop;
- an inverter stage coupled to the logic stage and including a further current limiter comprising a further D-mode feedback transistor having a source, a drain, a gate and a gate-source junction, the further current limiter further comprising a further component that generates a voltage drop, and a further feedback loop connecting the source of the further D-mode feedback transistor to the gate of the further D-mode feedback transistor via the further component that generates the voltage drop;
- and
- a driver stage coupled to the inverter stage and comprising E-mode transistors having a source, a drain and a gate, the E-mode transistors being connected in a totem pole.
1 more element
A circuit comprising:
- a combinational logic circuit having a plurality of logic inputs, a first reference terminal and a second reference terminal;
- a first D-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit;
- a first component that generates a voltage drop having a first terminal coupled to the source of the first D-mode transistor and a second terminal coupled to the second reference terminal of the combinational logic circuit;
- a first E-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit and the source coupled to the first reference terminal of the combinational logic circuit;
- a second D-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drain of the first D-mode transistor;
- a second component that generates a voltage drop having a first terminal coupled to the source of the second D-mode transistor and a second terminal coupled to the drain of the first E-mode transistor;
- a second E-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drains of the first and second D-mode transistors;
- and
- a third E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the first E-mode transistor, the source coupled to the source of the first E-mode transistor and the first reference terminal of the combinational logic circuit, and the drain coupled to the source of the second E-mode transistor.
6 more elements
A circuit using GaAs technology, the circuit comprising:
- a combinational logic circuit having a plurality of logic inputs, a first reference terminal and a second reference terminal;
- a first D-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit;
- a fourth E-mode transistor having a source, a drain and a gate, the gate coupled to source of the first D-mode transistor;
- a sixth E-mode transistor having a source, a drain and a gate, the source being coupled to the second reference terminal of the combinational logic circuit;
- a first E-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit and the source coupled to the first reference terminal of the combinational logic circuit;
- a second D-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drain of the first D-mode transistor;
- a fifth E-mode transistor having a source, a drain and a gate, the gate being coupled to the source of the second D-mode transistor;
- a seventh E-mode transistor having a source, a drain and a gate, the source being coupled to the drain of the first E-mode transistor;
- a second E-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drains of the first and second D-mode transistors;
- a third E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the first E-mode transistor, the source coupled to the source of the first E-mode transistor and the first reference terminal of the combinational logic circuit, and the drain coupled to the source of the second E-mode transistor;
- a diode with a first terminal coupled to the drains of the first and second D-mode transistors and the drain of the second E-mode transistor and a second terminal coupled to the gate of the second E-mode transistor;
- a third D-mode transistor having a source, a drain and a gate, the drain coupled to the drains of the first and second D-mode transistors and the gate coupled to the source of the second E-mode transistor and the drain of the third E-mode transistor;
- and
- an eighth E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the third D-mode transistor and the source coupled to the sources of the first and third E-mode transistors.
11 more elements
Dependencies are inferred from the claim text.