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US 2012/0267791 A1Published application
Multi chip package, manufacturing method thereof, and memory system having the multi chip package
AssigneeSamsung Electronics Co., Ltd.
InventorsByung-Hyun LEE, Hoon LEE
Life of this patent
Estimating the term…
Abstract
A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.
Claims18
A multi-chip package comprising:
- a plurality of chips comprising at least one bad chip and at least one good chip that are stacked;
- and
- a plurality of through electrodes each penetrating the plurality of chips,
- wherein a logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.
1 more element
A multi-chip package manufacturing method comprising:
- stacking at least one good chip on at least one bad chip included in a plurality of bonded wafers;
- connecting the at least one bad chip with the at least one good chip electrically;
- and
- isolating a logic circuit included in the at least one bad chip from the at least one good chip electrically.
1 more element
A multi-chip package comprising:
- a first wafer comprising a plurality of first chips;
- a second wafer comprising a plurality of second chips, the second wafer being bonded to the first wafer;
- a good chip configured to electrically replace a bad chip located on one of the first wafer or the second wafer, without removing the bad chip from the first wafer or the second wafer on which is the bad chip is located.
-20. (canceled)
Dependencies are inferred from the claim text.