Vias in porous substrates

An interconnection substrate, comprising:

• a substrate having an effective CTE less than 8 ppm/° C., having a first surface and a second surface remote therefrom, the substrate having a plurality of openings extending between the first and second surfaces, the openings arranged in a symmetric or asymmetric distribution across an area of the first surface, with at least m openings spaced apart in a first direction along the first surface and n openings spaced apart in a second direction along the first surface transverse to the first direction, each of m and n being greater than 1;
• pluralities of first and second conductive interconnects, each conductive interconnect extending within a respective one of the openings and having ends adjacent the first and second surfaces;
• and
• sets of first conductive contacts and sets of second conductive contacts exposed at the first and second surfaces for interconnection with an external element, each set of the first conductive contacts including a first conductive contact exposed at the first surface and a first conductive contact exposed at the second surface, with the plurality of first conductive interconnects electrically connecting such set, each set of the second conductive contacts including a second conductive contact exposed at the first surface and a second conductive contact exposed at the second surface, with the plurality of second conductive interconnects electrically connecting such set,
• wherein the plurality of first conductive interconnects is separated from the plurality of second conductive interconnects in a horizontal direction substantially parallel to the first surface by an insulating member extending within at least one of the plurality of openings between the first and second surfaces and at least partially filled with an insulating dielectric material.

An interconnection substrate, comprising:

• a substrate having an effective CTE less than 8 ppm/° C., having a first surface and a second surface remote therefrom, the substrate having a plurality of openings extending between the first and second surfaces;
• a plurality of conductive interconnects extending within respective ones of a first subset of the openings;
• and
• an insulating dielectric material extending at least partially within respective ones of a second subset of the openings.

An interconnection substrate, comprising:

• a substrate having an effective CTE less than 8 ppm/° C., having a first surface and a second surface remote therefrom, the substrate having a plurality of openings extending between the first and second surfaces through a region of first material, each opening having first and second ends adjacent the first and second surfaces, respectively;
• a plurality of conductive interconnects extending within respective ones of a first subset of the openings, each conductive interconnect having first and second ends adjacent the first and second surfaces;
• and
• a plurality of insulating members extending within respective ones of a second subset of the openings, each insulating member having first and second opposed end portions within the respective opening adjacent the first and second surfaces, the first and second end portions consisting essentially of a dielectric material, the dielectric material being other than the first material,
• wherein at least two of the conductive interconnects are separated from one another by at least one of the insulating members such that no current can flow through the insulating member between the at least two conductive interconnects and no current can flow through the insulating member between the first and second end portions.

A method of fabricating a microelectronic unit, comprising:

• forming a plurality of openings extending from a first surface of a semiconductor substrate towards a second surface remote therefrom, the openings arranged in a symmetric or asymmetric distribution across an area of the first surface, with at least m openings spaced apart in a first direction along the first surface and n openings spaced apart in a second direction along the first surface transverse to the first direction, each of m and n being greater than 1, the substrate embodying a plurality of active semiconductor devices, the substrate having a plurality of conductive pads exposed at the second surface;
• forming pluralities of first and second conductive interconnects extending within respective ones of the openings;
• and
• forming first and second conductive vias electrically connected with respective first and second pads of the plurality of conductive pads, each first conductive interconnect being electrically connected to the first conductive via, each second conductive interconnect being electrically connected to the second conductive via.

A method of fabricating a microelectronic unit, comprising:

• forming a plurality of openings extending from a first surface of a semiconductor substrate towards a second surface remote therefrom, the openings arranged in a symmetric or asymmetric distribution across an area of the first surface, with at least m openings spaced apart in a first direction along the first surface and n openings spaced apart in a second direction along the first surface transverse to the first direction, each of m and n being greater than 1, the substrate embodying a plurality of active semiconductor devices, the substrate having a plurality of conductive pads exposed at the second surface;
• removing material of the semiconductor substrate extending between respective ones of a first and second subset of the openings to form respective first and second cavities occupying areas coextensive with the respective first and second subsets of the openings;
• forming first and second conductive interconnects extending within the respective first and second cavities;
• and
• forming first and second conductive vias electrically connected with respective first and second pads of the plurality of conductive pads, the first and second conductive vias being electrically connected with the respective first and second conductive interconnects.

A method of fabricating an interconnection substrate, comprising:

• forming a plurality of openings extending from a first surface of a substrate having an effective CTE less than 8 ppm/° C. towards a second surface remote therefrom, the openings arranged in a symmetric or asymmetric distribution across an area of the first surface, with at least m openings spaced apart in a first direction along the first surface and n openings spaced apart in a second direction along the first surface transverse to the first direction, each of m and n being greater than 1;
• forming pluralities of first and second conductive interconnects, each conductive interconnect extending within a respective one of the openings and having ends adjacent the first and second surfaces;
• and
• forming sets of first conductive contacts and sets of second conductive contacts exposed at the first and second surfaces for interconnection with an external element, each set of the first conductive contacts including a first conductive contact exposed at the first surface and a first conductive contact exposed at the second surface, with the plurality of first conductive interconnects electrically connecting such set, each set of the second conductive contacts including a second conductive contact exposed at the first surface and a second conductive contact exposed at the second surface, with the plurality of second conductive interconnects electrically connecting such set.

A method of fabricating an interconnection substrate, comprising:

• forming a plurality of openings extending from a first surface of a substrate having an effective CTE less than 8 ppm/° C. towards a second surface remote therefrom, the openings arranged in a symmetric or asymmetric distribution across an area of the first surface, with at least m openings spaced apart in a first direction along the first surface and n openings spaced apart in a second direction along the first surface transverse to the first direction, each of m and n being greater than 1;
• removing material of the semiconductor substrate extending between respective ones of a first and second subset of the openings to form respective first and second cavities occupying areas coextensive with the respective first and second subsets of the openings;
• forming first and second conductive interconnects extending within the respective first and second cavities, each of the first and second conductive interconnects having ends adjacent the first and second surfaces;
• and
• forming sets of first conductive contacts and sets of second conductive contacts exposed at the first and second surfaces for interconnection with an external element, each set of the first conductive contacts including a first conductive contact exposed at the first surface and a first conductive contact exposed at the second surface, with the first conductive interconnect electrically connecting such set, each set of the second conductive contacts including a second conductive contact exposed at the first surface and a second conductive contact exposed at the second surface, with the second conductive interconnect electrically connecting such set.