Decoupling capacitors recessed in shallow trench isolation

A method for fabricating a capacitor, comprising:

• providing a semiconductor substrate structure having a top surface;
• forming a shallow trench opening in the semiconductor substrate structure by selectively removing a portion of the semiconductor substrate structure in a first region to define bottom and sidewall surfaces of a trench opening where the bottom surface exposes a semiconductor region in the semiconductor substrate structure which forms at least part of a bottom capacitor plate;
• forming one or more dielectric layers on bottom and sidewall surfaces of the trench opening by forming a dielectric layer on the bottom and sidewall surfaces in the trench opening, and anisotropically etching the dielectric layer in the trench opening to partially etch the dielectric layer to form an isolation dielectric layer on the sidewall surface of the trench opening that is at least twice as thick as a capacitor dielectric layer on the bottom surface of the trench opening;
• forming a recessed conductive layer on the one or more dielectric layers on the bottom surface of the trench opening as a top capacitor plate, where the recessed conductive layer has a top surface which is below the top surface of the semiconductor substrate structure;
• and
• forming a shallow trench isolation layer over the top capacitor plate, the shallow trench isolation layer having a bottom surface which is below the top surface of the semiconductor substrate structure.

An integrated circuit trench capacitor structure, comprising:

• a first capacitor plate located in a doped semiconductor layer to be located below a trench formed in a substrate structure having a top surface;
• a capacitor dielectric layer located on the first capacitor plate and in the trench;
• and
• a recessed second capacitor plate located on the capacitor dielectric layer and made from a conductive material in the trench, where the recessed second capacitor plate has a top surface which is located below the top surface of the substrate structure and which is covered with a shallow trench isolation layer having a bottom surface which is below the top surface of the substrate structure and surrounded by an insulation layer formed on sidewall surfaces of the trench that is thicker than the capacitor dielectric layer to provide electrical isolation from adjacent semiconductor material.