Integrated circuit device and method of manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDer-Chyang Yeh, Shang-Yun Hou
Life of this patent
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Abstract
Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.
Claims20
An integrated circuit device comprising:
- a semiconductor substrate;
- a dielectric layer disposed over the semiconductor substrate;
- a passive element disposed over the dielectric layer;
- and
- an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area.
A method comprising:
- providing a semiconductor substrate;
- forming a dielectric layer over the semiconductor substrate;
- forming a hard mask layer over the dielectric layer, wherein the hard mask layer has an opening;
- forming a plurality of trenches by etching the dielectric layer and the semiconductor substrate within the opening of the hard mask layer;
- forming an insulating material within the plurality of trenches, wherein the insulating material includes a void area;
- forming a interlayer dielectric layer over the dielectric layer;
- and
- forming a passive element over the interlayer dielectric layer.
An integrated circuit structure comprising
- a semiconductor substrate;
- a dielectric layer disposed over the semiconductor substrate;
- an interlayer dielectric layer disposed over the dielectric layer;
- an inter-metal dielectric layer disposed over the interlayer dielectric layer;
- a magnetic flux generating electrical structure disposed over the inter-metal dielectric layer;
- a plurality of trenches arranged in a pattern formed through the dielectric layer and extending into the semiconductor substrate;
- an insulating material disposed within the plurality of trenches;
- and
- a void area disposed within the insulating material,
- wherein the plurality of trenches are configured to inhibit eddy current induced in the semiconductor substrate by a magnetic flux of the magnetic flux generating electrical structure.
Dependencies are inferred from the claim text.