Mos semiconductor device and methods for its fabrication
AssigneeGlobalfoundries Inc.
InventorSuresh VENKATESAN
Life of this patent
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Abstract
An MOS device having a selectively formed channel region and methods for its fabrication are provided. One such method includes forming a mask defining a gate region overlying a surface of a semiconductor substrate. Source and drain regions are formed in the semiconductor substrate in alignment with the gate region and an enhanced doping sub-surface impurity region is formed in the semiconductor substrate using the mask as a doping mask. A gate electrode is then formed overlying the semiconductor substrate in alignment with the gate region by using the mask as a gate alignment mask.
Claims20
A method for fabricating an MOS device comprising:
- depositing a layer of dummy gate material overlying a surface of a semiconductor substrate and patterning the dummy gate material to form a dummy gate;
- implanting spaced apart source and drain regions in alignment with the dummy gate;
- depositing a gap fill material overlying the semiconductor substrate and the dummy gate;
- removing a portion of the gap fill material to expose a top surface of the dummy gate;
- removing the dummy gate to form a recess extending through the gap fill material;
- implanting conductivity determining ions through the recess and into the semiconductor substrate to form an impurity doped channel region between the spaced apart source and drain regions;
- exposing a portion of the surface of the semiconductor substrate overlying the impurity doped channel;
- and
- forming a gate insulator and gate electrode overlying the portion of the surface.
A method for fabricating an MOS device comprising:
- forming a mask defining a gate region overlying a surface of a semiconductor substrate;
- forming source and drain regions in the semiconductor substrate in alignment with the gate region;
- forming an enhanced doping sub-surface impurity region in the semiconductor substrate using the mask as a doping mask;
- and
- forming a gate electrode overlying the semiconductor substrate and in alignment with the gate region using the mask as a gate alignment mask.
An MOS device comprising:
- a gate electrode overlying a semiconductor substrate;
- spaced apart source and drain regions formed in the semiconductor substrate and aligned with the gate electrode;
- and
- an impurity doped channel region underlying the gate electrode and spaced apart from the source and drain regions.
Dependencies are inferred from the claim text.