US 2012/0267701 A1 · THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Abstract

Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

Claims20

Dependent claims

A nonvolatile memory device, comprising:

a vertical stack of nonvolatile memory cells on a substrate, said vertical stack of nonvolatile memory cells comprising a first nonvolatile memory cell having a first gate pattern therein separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness and also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

Dependencies are inferred from the claim text.

Facts

Application

13/425,584Filed 21 Mar 2012

Priority

KR 10-2011-003635319 Apr 2011

Published

25 Oct 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/02
Details of stores covered by group G11C11/00: disposition of storage elements, e.g. in the form of a matrix array
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Three dimensional semiconductor memory devices and methods of manufacturing the same

Life of this patent

Three dimensional semiconductor memory devices and methods of manufacturing the same

Life of this patent

Abstract

Claims20