US 2012/0267689 A1 · Memory with Off-Chip Controller

Abstract

An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Claims20

Dependent claims

A method for manufacturing a memory device, the method comprising:

forming a memory circuit comprising a plurality of memory cells, the memory circuit having a first interconnect surface with a first set of interconnect locations, interconnect locations in the first set of interconnect locations electrically coupled to corresponding memory cells in the plurality of memory cells;
forming a peripheral circuit configured to provide control signals for operation of the memory circuit, the peripheral circuit having a second interconnect surface with a second set of interconnect locations;
and
joining the first interconnect surface of the memory circuit to the second interconnect surface of the peripheral circuit.

1 more element

Dependencies are inferred from the claim text.

Memory with Off-Chip Controller

Life of this patent

Memory with Off-Chip Controller

Life of this patent

Abstract

Claims20