US 2012/0260225 A1 · Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits

Abstract

A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Claims20

Dependent claims

A method of extracting a capacitance, the method comprising:

reading a technology file into an extraction system;
and
reading a circuit layout into said extraction system;
wherein said technology file includes a capacitance table;
wherein a connector capacitance in said capacitance table is derived from an effective connector area table;
and
wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof.

4 more elements

A method of conducting testing and simulation, the method comprising:

reading a technology file into an extraction system;
and
reading a circuit layout into said extraction system;
processing a geometry of said circuit layout in said extraction system;
and
extracting parasitic capacitance by pattern-matching a connector configuration in said technology file from a pattern in said circuit layout;
wherein said technology file includes a capacitance table;
wherein a connector capacitance in said capacitance table is derived from an effective connector area table;
and
wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/527,096Filed 19 Jun 2012

Priority

29 Jun 2007

Published

11 Oct 2012

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/2853
Testing of integrated circuits [IC]: electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
H10P 74/277
Structural arrangements therefor: circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or…
G01R 31/2884
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
G01R
Measuring electric variables

Family

Application60/947,269Us provisional application · filed 29 Jun 2007

Application11/865,304Division · filed 1 Oct 2007

Application12/893,870Division · filed 29 Sep 2010

Application13/527,096Division

US 2009/0007035 A1Published application

US 2011/0023003 A1Published application

US 7,818,698 B2Related patent

US 8,214,784 B2Related patent

US 8,572,537 B2Related patent

US 2012/0260225 A1This patent

From the US filing history. Foreign family members aren’t listed.

Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits

Life of this patent

Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits

Life of this patent

Abstract

Claims20