US 2012/0260083 A1 · Adjusting Device Performance over Multiple Time Domains

Abstract

Adjusting processor performance based on processing profiles. The method may determine that a process has entered a processing state after an idle state. In response to entering the processing state the processing time of the processor may be monitored. In response to the processing time exceeding a first threshold of time, the performance of the processor may be increased from a first level to a second level. In response to the processing time exceeding a second threshold time, the performance of the processor may be decreased from the second level to a third level. In response to the processing time exceeding a third threshold time, the performance of the processor may be increased from the third level to a fourth level. In response to the processing time exceeding a fourth threshold time, the performance of the processor may be decreased from the fourth level to a fifth level.

Claims25

Dependent claims

A method for controlling performance of a processor of a device, comprising:

determining that the processor has entered a processing state after an idle state, wherein the processor initially operates at a first performance level in the processing state;
in response to the processor entering the processing state, monitoring processing time of the processor since entering the processing state;
in response to the processing time exceeding a first threshold of time, increasing performance of the processor to a second processing level that is greater than the first processing level;
in response to the processing time exceeding a second threshold of time that is greater than the first threshold of time, decreasing performance of the processor to a third processing level that is less than the second processing level but greater than the first level;
in response to the processing time exceeding a third threshold of time that is greater than the second threshold of time, increasing performance of the processor to a fourth processing level that is greater than the third processing level.

2 more elements

A system for controlling processor performance, comprising:

one or more processors;
a power manager circuit coupled to the one or more processors, wherein the power manager circuit is configured to control a voltage level of the one or more processors;
one or more memory mediums coupled to the one or more processors, wherein the one or more memory mediums store program instructions executable by at least one of the one or more processors to:
determine that at least a first processor of the one or more processors has exited an idle state;
in response to the first processor exiting the idle state, monitor processing time of at least the first processor since existing the idle state;
in response to the processing time exceeding a first threshold of time, provide a first signal to the power manager circuit, wherein, in response to the first signal, the power manager circuit is configured to increase the voltage level of at least the first processor from a first voltage level to a second voltage level;
and
in response to the processing time exceeding a second threshold of time that is greater than the first threshold of time, provide a second signal to the power manager circuit, wherein, in response to the second signal, the power manager circuit is configured to decrease the voltage level of at least the first processor from the second voltage level to a third voltage level, wherein the third voltage level is greater than the first voltage level;
in response to the processing time exceeding a third threshold of time that is greater than the second threshold of time, provide a third signal to the power manager circuit, wherein, in response to the third signal, the power manager circuit is configured to increase the voltage level of at least the first processor from the third voltage level to a fourth voltage level.

6 more elements

A non-transitory, computer-accessible memory medium storing program instructions for controlling performance of a circuit, wherein the program instructions are executable to:

determine that the circuit has entered a processing state after an idle state, wherein the circuit initially operates at a first performance level in the processing state;
in response to the circuit entering the processing state, monitor processing time of the circuit since entering the processing state;
in response to the processing time exceeding a first threshold of time, increase performance of the circuit to a second processing level that is greater than the first processing level, wherein the second processing level is above a sustainable processing level;
in response to the processing time exceeding a second threshold of time that is greater than the first threshold of time, decrease performance of the circuit to a third processing level that is less than the second processing level but greater than the first level, wherein the third processing level is a sustainable processing level;
in response to the processing time exceeding a third threshold of time that is greater than the second threshold of time, increase performance of the circuit to the second processing level, wherein the fourth processing level is above the sustainable processing level.

2 more elements

Dependencies are inferred from the claim text.

Adjusting Device Performance over Multiple Time Domains

Life of this patent

Adjusting Device Performance over Multiple Time Domains

Life of this patent

Abstract

Claims25