Efficient conditional alu instruction in read-port limited register file microprocessor

A microprocessor having architectural condition flags, wherein the microprocessor performs an architectural instruction that instructs the microprocessor to perform a shift operation on a first source operand to generate a first result, to perform a second operation on the first result and a second operand to generate a second result, and to write the second result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising:

• a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into at least first and second microinstructions;
• and
• an execution pipeline, that executes the microinstructions received from the hardware instruction translator;
• wherein in response to the first microinstruction, the execution pipeline:
• performs the shift operation on the first source operand to generate the first result;
• wherein in response to the second microinstruction, the execution pipeline:
• writes the destination register with the second result, if the architectural condition flags satisfy the condition;
• and
• writes the destination register with the current value of the destination register, if the architectural condition flags do not satisfy the condition.

A method for a microprocessor, having architectural condition flags, to perform an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the method comprising:

• translating the architectural instruction into first and second microinstructions, wherein said translating is performed by a hardware instruction translator of the microprocessor;
• and
• executing the microinstructions received from the hardware instruction translator, wherein said executing is performed by an execution pipeline of the microprocessor;
• wherein said executing the first microinstruction comprises:
• performing the operation on the source operands to generate the result;
• wherein said executing the second microinstruction comprises:
• writing the destination register with the result generated by the first microinstruction, if the architectural condition flags satisfy the condition;
• and
• writing the destination register with the current value of the destination register, if the architectural condition flags do not satisfy the condition.

A method for a microprocessor, having architectural condition flags, to perform an architectural instruction that instructs the microprocessor to perform a shift operation on a first source operand to generate a first result, to perform a second operation on the first result and a second operand to generate a second result, and to write the second result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the method comprising:

• translating the architectural instruction into at least first and second microinstructions, wherein said translating is performed by a hardware instruction translator of the microprocessor;
• and
• executing the microinstructions received from the hardware instruction translator, wherein said executing is performed by an execution pipeline of the microprocessor;
• wherein said executing the first microinstruction comprises:
• performing the shift operation on the first source operand to generate the first result;
• wherein said executing the second microinstruction comprises:
• writing the destination register with the second result, if the architectural condition flags satisfy the condition;
• and
• writing the destination register with the current value of the destination register, if the architectural condition flags do not satisfy the condition.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor having architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the computer readable program code comprising:
• first program code for specifying a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions;
• and
• second program code for specifying an execution pipeline, that executes the microinstructions received from the hardware instruction translator;
• wherein in response to the first microinstruction, the execution pipeline:
• performs the operation on the source operands to generate the result;
• wherein in response to the second microinstruction, the execution pipeline:
• writes the destination register with the result generated by the first microinstruction, if the architectural condition flags satisfy the condition;
• and
• writes the destination register with the current value of the destination register, if the architectural condition flags do not satisfy the condition.