Emulation of execution mode banked registers

A method for operating a microprocessor that includes a plurality of processor modes comprising a user mode and a plurality of exception modes, wherein the microprocessor also comprises at least one execution unit that performs arithmetic operations on operands specified by program instructions, the method comprising:

• while operating the microprocessor in a current mode of the plurality of processor modes, providing a first set of operands from a first set of storage elements to the execution unit to perform arithmetic operations;
• entering a new mode of the plurality of processor modes from the current mode, comprising:
• saving the first set of operands held in the first set of storage elements to a second set of storage elements associated with the current mode;
• and
• restoring to the first set of storage elements a second set of operands held in a third set of storage elements associated with the new mode;
• and
• while operating the microprocessor in the new mode, providing the second set of operands from the first set of storage elements to the execution unit to perform arithmetic operations.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising:
• first program code for specifying a plurality of processor modes, comprising a user mode and a plurality of exception modes;
• second program code for specifying at least one execution unit, that performs arithmetic operations on operands specified by program instructions;
• third program code for specifying a first set of storage elements, coupled to the execution unit, wherein the first set of storage elements holds a first subset of the operands and provides the first subset of the operands to the execution unit;
• fourth program code for specifying a second set of storage elements associated with each of the plurality of processor modes, wherein the second sets of storage elements hold a second subset of the operands, wherein the second sets of storage elements are incapable of directly providing the second subset of the operands to the execution unit;
• and
• fifth program code for specifying logic, wherein to enter a new mode of the plurality of processor modes from a current mode of the plurality of processor modes, the logic saves the first subset of the operands held in the first set of storage elements to the second set of storage elements associated with the current mode and restores to the first set of storage elements the second subset of the operands held in the second set of storage elements associated with the new mode.