Conditional alu instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor

A method for a microprocessor, having architectural condition flags, to perform an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the method comprising:

• translating the architectural instruction into first and second microinstructions, wherein said translating is performed by a hardware instruction translator of the microprocessor;
• and
• executing the microinstructions received from the hardware instruction translator, wherein said executing is performed by an execution pipeline of the microprocessor;
• wherein said executing the first microinstruction comprises:
• performing the operation on the source operands to generate the result;
• determining whether the architectural condition flags satisfy the condition;
• and
• updating a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition;
• wherein said executing the second microinstruction comprises:
• if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, updating the destination register with the result;
• and
• if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags do not satisfy the condition, updating the destination register with the current value of the destination register.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor having architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if the architectural condition flags satisfy a condition specified in the architectural instruction, the computer readable program code comprising:
• first program code for specifying a register, that includes storage for the architectural condition flags and also contains storage for a non-architectural indicator;
• second program code for specifying a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions;
• and
• third program code for specifying an execution pipeline, that executes the microinstructions received from the hardware instruction translator;
• wherein in response to the first microinstruction, the execution pipeline:
• performs the operation on the source operands to generate the result;
• determines whether the architectural condition flags satisfy the condition;
• and
• updates the non-architectural indicator to indicate whether the architectural condition flags satisfy the condition;
• wherein in response to the second microinstruction, the execution pipeline:
• if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, updates the destination register with the result;
• and
• if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags do not satisfy the condition, updates the destination register with the current value of the destination register.