Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• an external interface;
• at least one level one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit;
• a level two memory connected to said at least one level one cache, said level two memory including
• a level two unified cache temporarily storing instructions and data for supply of instructions and data to said at least one level one cache, and
• a directly addressable memory;
• and
• a level two memory controller connected to said at least one level one cache, said level two memory and said external interface, said level two memory including
• a directly addressable memory read pipeline connected to said at least one level one cache receiving read requests for data stored in said directly addressable memory,
• a central processing unit write pipeline receiving central processing write requests to addressed stored in said directly addressable memory,
• an external cacheable pipeline receiving read accesses and write accesses to external memory at cacheable addresses, and
• an external non-cacheable pipeline receiving read accesses and write accesses to external memory at non-cacheable addresses.