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US 2012/0259908 A1Published application
Fast carry lookahead circuits
AssigneeMicrosemi SoC Corporation
InventorsVolker Hecht, Marcel Derevlean, Jonathan Greene
Life of this patent
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Abstract
A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
Claims7
A carry lookahead circuit for a fast carry adder comprising:
- a carry-in signal node;
- first, second, and third carry-input signal nodes;
- first, second, and third propagate signal nodes;
- first, second, and second local carry-out signal nodes;
- a carry-out signal node;
- a first buffer having an input and an output, the input coupled to the carry-in signal node and the output coupled to the first local carry-out signal node;
- a first multiplexer having a first data input coupled to the first carry-input signal node, a second data input coupled to the output of the first buffer, a control input coupled to the first propagate signal node, and an output coupled to the second local carry-out signal node;
- a second multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the first carry-input signal node, a control input coupled to the second propagate signal node, and an output;
- a third multiplexer having a first data input coupled to the third carry-input signal node, a second data input coupled to the output of the second multiplexer, and a
- an AND gate having a first input coupled to the first propagate input node, a second input coupled to the second propagate input node, a control input coupled to the third propagate signal node and an output;
- a fourth multiplexer having a first data input coupled to the output of the third multiplexer, a second data input coupled to the carry-in signal node, a control input coupled to the output of the AND gate, and an output coupled to the carry-out signal node;
- a fifth multiplexer having a first data input coupled to the second carry-input signal node, a second data input coupled to the output of the first multiplexer, a control input coupled to the second propagate signal node, and an output coupled to the third local carry-out signal node.
9 more elements
A carry lookahead circuit comprising:
- N stages, where N≧3;
- the carry lookahead circuit including separate carry-entrance and carry-exit paths;
- and
- wherein the carry lookahead circuit includes fewer than 3×N two-input multiplexers.
1 more element
Dependencies are inferred from the claim text.