Pipelined divide circuit for small operand sizes
AssigneeOracle International Corporation
InventorsChristopher H. Olson, Jeffrey S. Brooks
Life of this patent
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Abstract
A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.
Claims20
A circuit for performing a divide operation, the circuit comprising:
- a plurality of serially-connected stages, wherein each stage of said stages is configured to:
- receive as inputs on each clock cycle an effective divisor and a first partial remainder;
- generate as outputs on each clock cycle a second partial remainder and a plurality of quotient bits, wherein the second partial remainder is coupled to a subsequent stage;
- wherein each of a first and last stage of the plurality of stages comprises a restoring series architecture;
- and
- wherein each of one or more intermediate stages of the plurality of stages comprises a restoring parallel architecture.
A circuit comprising:
- a plurality of series of serially-connected stages, wherein each series is configured to perform a divide operation, and wherein the plurality of series are configured to concurrently perform a plurality of divide operations on a plurality of pairs of dividends and divisors to generate a plurality of quotients;
- wherein each series of the plurality of series comprises:
- a plurality of serially-connected stages, wherein each stage of the plurality of stages is configured to:
- receive as inputs an effective divisor and a first partial remainder on each clock cycle;
- generate as outputs a second partial remainder and a plurality of quotient bits on each clock cycle, wherein the second partial remainder is coupled to a subsequent stage;
- wherein each of a first and last stage of the plurality of stages comprises a restoring series architecture;
- and
- wherein each of one or more intermediate stages of the plurality of stages comprises a restoring parallel architecture.
A processing unit configured to perform divide operations, wherein the processing unit comprises:
- a plurality of serially-connected stages, wherein each stage of the plurality of stages is configured to:
- receive as inputs an effective divisor and a first partial remainder on each clock cycle;
- generate as outputs a second partial remainder and a plurality of quotient bits on each clock cycle, wherein the second partial remainder is coupled to a subsequent stage;
- wherein each of a first and last stage of the plurality of stages comprises a restoring series architecture;
- and
- wherein each of one or more intermediate stages of the plurality of stages comprises a restoring parallel architecture.
Dependencies are inferred from the claim text.