US 2012/0259575 A1 · INTEGRATED CIRCUIT CHIP INCORPORATING A TEST CIRCUIT THAT ALLOWS FOR ON-CHIP STRESS TESTING IN ORDER TO MODEL OR MONITOR DEVICE PERFORMANCE DEGRADATION

Abstract

Disclosed is an integrated circuit chip incorporating a test circuit having multiple logic blocks. Each logic block is a matrix of individually selectable, physically different, test devices in a specific class of devices. An embedded processor ensures that specific stress conditions are selectively applied to the test devices and further controls selective testing, by a sensor system, of the test devices to determine the impact of the applied stress conditions. In a laboratory or test system environment, accelerated stress conditions are selectively applied to the test devices and the testing results are used to model device performance degradation due to class-specific failure mechanisms. In the field, stress conditions are selectively applied to test devices so as to mimic stress conditions impacting active devices in use on the same chip and the testing results are used to indirectly monitor performance degradation of the active devices due to class-specific failure mechanisms.

Claims20

Dependent claims

An integrated circuit chip circuit comprising:

multiple logic blocks, each one of said multiple logic blocks being associated with a specific class of devices and comprising a matrix of individually selectable, physically different, test devices in said specific class;
a sensor system;
and
an embedded processor operatively connected to said multiple logic blocks and said sensor system, said embedded processor controlling selective stressing of said test devices by causing a specific test device to be subjected to specific stress conditions and further controlling selective testing of said test devices by causing said sensor system to determine an actual value of a specific electrical characteristic exhibited by said specific test device following application of said specific stress conditions.

1 more element

An integrated circuit chip incorporated into a product, said integrated circuit chip comprising:

at least one functional circuit comprising a plurality of active devices in use in said product;
and
a test circuit comprising:
multiple logic blocks, each one of said multiple logic blocks being associated with a specific class of devices and comprising a matrix of individually selectable, physically different, test devices in said specific class, said test devices being duplicates of said active devices;
a sensor system;
and
an embedded processor operatively connected to said multiple logic blocks and said sensor system,
said embedded processor controlling selective stressing of said test devices by causing a specific test device to be subjected to specific stress conditions and further controlling selective testing of said test devices by causing said sensor system to determine an actual value of a specific electrical characteristic exhibited by said specific test device following application of said specific stress conditions, said specific stress conditions approximating in-use stress conditions imparted on a corresponding active device, and
said embedded processor further being remote access service (RAS) enabled so as to allow for remote communication with said embedded processor.

6 more elements

Dependencies are inferred from the claim text.

Integrated circuit chip incorporating a test circuit that allows for on-chip stress testing in order to model or monitor device performance degradation

Life of this patent

Integrated circuit chip incorporating a test circuit that allows for on-chip stress testing in order to model or monitor device performance degradation

Life of this patent

Abstract

Claims20