Capacitor-less memory cell, device, system and method of making same
AssigneeMicron Technology, Inc.
InventorsFernando Gonzalez, Chandra V. Mouli
Life of this patent
Estimating the term…
Abstract
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
Claims20
A process of forming a capacitor-less memory cell, comprising:
- forming an active area from a bulk semiconductor substrate to be substantially physically isolated from the bulk semiconductor substrate by least one material extending laterally between the active area and the bulk semiconductor substrate;
- forming a read/write enable transistor vertically configured along at least one vertical side of an active area and including a gate, a source region, and a drain region commonly shared with a source region of a pass transistor;
- and
- forming the pass transistor in the active area, the pass transistor including the source region, and a drain region for coupling with a digit line and a gate for coupling with a word.
A process of forming a memory cell, comprising:
- forming a read/write enable transistor in a semiconductor substrate, the read/write enable transistor comprising a drain region and a source region;
- forming a pass transistor in the semiconductor substrate, the pass transistor comprising a drain region and a source region, the source region of the pass transistor common in an active area with the drain region of the read/write enable transistor;
- and
- forming the active area to be at least substantially physically isolated from the semiconductor substrate by at least one material and a gate of the read/write enable transistor extending at least laterally between a portion of the active area and the source region of the read/write enable transistor.
A process comprising:
- forming an active area by removing a portion of a bulk semiconductor substrate to form a lateral cavity below the active area;
- forming a vertically-oriented transistor;
- forming a horizontally-oriented transistor having a source region common with a drain region of the vertically-oriented transistor in the active area;
- and
- forming a gate for the vertically-oriented transistor by forming at least one material within the lateral cavity.
Dependencies are inferred from the claim text.