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US 2012/0258574 A1Published application
Couplings within memory devices
AssigneeMicron Technology, Inc.
InventorsAkira GODA, Seiichi Aritome
Life of this patent
Estimating the term…
Abstract
A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.
Claims36
A method of forming a memory device, comprising:
- forming a first bit line at a first vertical level;
- forming a second bit line at a second vertical level different from the first vertical level;
- coupling the first bit line to a first source/drain region of a first multiplexer gate;
- coupling the second bit line to a first source/drain region of a second multiplexer gate;
- and
- coupling second source/drain regions of the first and second multiplexer gates to an input of a sensing device formed at the second vertical level.
3 more elements
A method of forming a memory device, comprising:
- forming first and second bit lines at a first vertical level;
- coupling the first bit line to a first source/drain region of a first multiplexer gate;
- coupling the second bit line to a first source/drain region of a second multiplexer gate;
- and
- coupling second source/drain regions of the first and second multiplexer gates to an input of a sensing device formed at a second vertical level different than the first vertical level.
2 more elements
A method of forming a memory device, comprising:
- forming first and second bit lines at a first vertical level;
- forming third and fourth bit lines at a second vertical level different from the first vertical level;
- coupling the first bit line to a first source/drain region of a first multiplexer gate;
- coupling the third bit line to a first source/drain region of a second multiplexer gate;
- coupling second source/drain regions of the first and second multiplexer gates to an input of a sensing device formed at the first vertical level;
- coupling the second bit line to a first source/drain region of a third multiplexer gate;
- coupling the fourth bit line to a first source/drain region of a fourth multiplexer gate;
- and
- coupling second source/drain regions of the third and fourth multiplexer gates to an input of a sensing device formed at the second vertical level.
6 more elements
A method of forming a memory device, comprising:
- forming first and second bit lines at a first vertical level;
- forming third and fourth bit lines at a second vertical level different from the first vertical level;
- coupling the first bit line to a first source/drain region of a first multiplexer gate;
- coupling the third bit line to a first source/drain region of a second multiplexer gate;
- coupling second source/drain regions of the first and second multiplexer gates to an input of a first sensing device formed at the first vertical level;
- coupling the second bit line to a first source/drain region of a third multiplexer gate;
- coupling the fourth bit line to a first source/drain region of a fourth multiplexer gate;
- and
- coupling second source/drain regions of the third and fourth multiplexer gates to an input of a second sensing device formed at the first vertical level.
6 more elements
A method of forming a memory device, comprising:
- forming first and second bit lines at a first vertical level;
- forming third and fourth bit lines at a second vertical level different from the first vertical level;
- coupling the first bit line to a first source/drain region of a first multiplexer gate;
- coupling the second bit line to a first source/drain region of a second multiplexer gate;
- coupling second source/drain regions of the first and second multiplexer gates to an input of a sensing device formed at the second vertical level;
- coupling the third bit line to a first source/drain region of a third multiplexer gate;
- coupling the fourth bit line to a first source/drain region of a fourth multiplexer gate;
- and
- coupling second source/drain regions of the third and fourth multiplexer gates to an input of a sensing device formed at the first vertical level.
6 more elements
A method of forming a memory device, comprising:
- forming first and second multiplexer gates;
- forming first and second source/drain regions for the first and second multiplexer gates at a first vertical level;
- forming a first contact coupled to the first source/drain region of the first multiplexer gate;
- forming a second contact coupled to the first source/drain region of the second multiplexer gate;
- forming a third contact coupled to the second source/drain regions of the first and second multiplexer gates;
- forming a first wiring layer at a second vertical level different than the first vertical level, wherein forming the first wiring layer comprises forming first and second bit lines of the first wiring layer respectively coupled to the first and second contacts;
- forming a second wiring layer at a third vertical level different than the first and second vertical levels, the second wiring layer coupled to the third contact;
- and
- coupling the second wiring layer to an input of a sensing device formed at the second vertical level.
6 more elements
A method of forming a memory device, comprising:
- forming first and second multiplexer gates;
- forming first and second source/drain regions for the first and second multiplexer gates at a first vertical level;
- forming a first contact coupled to the first source/drain region of the first multiplexer gate;
- forming a second contact coupled to the first source/drain region of the second multiplexer gate;
- forming a third contact coupled to the second source/drain regions of the first and second multiplexer gates;
- forming a first wiring layer at a second vertical level different than the first vertical level, wherein forming the first wiring layer comprises forming a bit line and a second line of the first wiring layer, the bit line of the first wiring layer coupled to the first contact and the second line of the first wiring layer coupled to the third contact;
- forming a second wiring layer at a third vertical level different than the first and second vertical levels, wherein forming the second wiring layer comprises forming a bit line of the second wiring layer coupled to the second contact;
- and
- coupling the second line of the first wiring layer to an input of a sensing device formed at the first vertical level.
6 more elements
A method of forming a memory device, comprising:
- forming first and second multiplexer gates;
- forming first and second source/drain regions for the first and second multiplexer gates at a first vertical level;
- forming a first contact coupled to the first source/drain region of the first multiplexer gate;
- forming a second contact coupled to the first source/drain region of the second multiplexer gate;
- forming a third contact coupled to the second source/drain regions of the first and second multiplexer gates;
- forming a first wiring layer at a second vertical level, comprising a bit line of the first wiring layer coupled to the first contact, the second vertical level different than the first vertical level;
- forming a second wiring layer at a third vertical level different than the first and second vertical levels, wherein forming the second wiring layer comprises forming a bit line and a second line of the second wiring layer, the bit line of the second wiring layer coupled to the second contact and the second line of the second wiring layer coupled to the third contact;
- and
- coupling the second line of the second wiring layer to an input of a sensing device formed at the second vertical level.
6 more elements
A method of forming a memory device, comprising:
- forming first, second, third, and fourth multiplexer gates;
- forming first and second source/drain regions for the first, second, third, and fourth multiplexer gates at a first vertical level;
- forming a first contact coupled to the first source/drain region of the first multiplexer gate;
- forming a second contact coupled to the first source/drain region of the second multiplexer gate;
- forming a third contact coupled to the second source/drain regions of the first and second multiplexer gates;
- forming a fourth contact coupled to the first source/drain region of the third multiplexer gate;
- forming a fifth contact coupled to the first source/drain region of the fourth multiplexer gate;
- forming a sixth contact coupled to the second source/drain regions of the third and fourth multiplexer gates;
- forming a first wiring layer at a second vertical level different than the first vertical level, wherein forming the first wiring level comprises forming first and second bit lines and a third line of the first wiring layer respectively coupled to the first, second, and third contacts;
- forming a second wiring layer at a third vertical level different than the first and second vertical levels, wherein forming the second wiring layer comprises forming first and second bit lines and a third line of the second wiring layer respectively coupled to the fourth, fifth, and sixth contacts;
- coupling the third line of the first wiring layer to an input of a first sensing device formed at the first vertical level;
- and
- coupling the third line of the second wiring layer to an input of a second sensing device formed at the second vertical level.
10 more elements
A method of forming a memory device, comprising:
- forming first, second, third, and fourth multiplexer gates;
- forming first and second source/drain regions for the first, second, third, and fourth multiplexer gates at a first vertical level;
- forming a first contact coupled to the first source/drain region of the first multiplexer gate;
- forming a second contact coupled to the first source/drain region of the second multiplexer gate;
- forming a third contact coupled to the second source/drain regions of the first and second multiplexer gates;
- forming a fourth contact coupled to the first source/drain region of the third multiplexer gate;
- forming a fifth contact coupled to the first source/drain region of the fourth multiplexer gate;
- forming a sixth contact coupled to the second source/drain regions of the third and fourth multiplexer gates;
- forming a first wiring layer at a second vertical level different than the first vertical level, wherein forming the first wiring layer comprises forming first and second bit lines and a third line of the first wiring layer respectively coupled to the first, fourth, and third contacts;
- forming a second wiring layer at a third vertical level different than the first and second vertical levels, wherein forming the second wiring layer comprises forming first and second bit lines and a third line of the second wiring layer respectively coupled to the second, fifth, and sixth contacts;
- coupling the third line of the first wiring layer to an input of a first sensing device formed at the first vertical level;
- and
- coupling the third line of the second wiring layer to an input of a second sensing device formed at the second vertical level.
10 more elements
A method of forming a memory device, comprising:
- forming first, second, third, and fourth multiplexer gates;
- forming first and second source/drain regions for the first, second, third, and fourth multiplexer gates at a first vertical level;
- forming a first contact coupled to the first source/drain region of the first multiplexer gate;
- forming a second contact coupled to the first source/drain region of the second multiplexer gate;
- forming a third contact coupled to the second source/drain regions of the first and second multiplexer gates;
- forming a fourth contact coupled to the first source/drain region of the third multiplexer gate;
- forming a fifth contact coupled to the first source/drain region of the fourth multiplexer gate;
- forming a sixth contact coupled to the second source/drain regions of the third and fourth multiplexer gates;
- forming a first wiring layer at a second vertical level different than the first vertical level, wherein forming the first wiring layer comprises forming first and second bit lines and third and fourth lines of the first wiring layer respectively coupled to the first, fourth, third, and sixth contacts;
- forming a second wiring layer at a second vertical level different than the first and second vertical levels, wherein forming the second wiring layer comprises forming first and second bit lines of the second wiring layer respectively coupled to the second and fifth contacts;
- and
- respectively coupling the third and fourth lines of the first wiring layer to an input of a first sensing device formed at the first vertical level and an input of a second sensing device formed at the first vertical level.
9 more elements
Dependencies are inferred from the claim text.