Method to avoid fixed pattern noise within backside illuminated (bsi) complementary metal-oxide-semiconductor (cmos) sensor array

#In semiconductor technologies, backside illuminated image sensors (BSIs) are used for sensing a volume of light projected towards a backside surface of a substrate. During fabrication of BSIs, an ion implantation is applied to the backside of the substrate, and a laser annealing process is further applied to the backside of the substrate to activate the implanted dopant. Either a scan-type laser or a step-type laser may be used to perform the annealing process after the ion implantation. However, when the scan-type laser source is used, a periodic defect, such as fixed pattern noise (FPN), is introduced into the BSIs. Furthermore, both the scan-type laser and the step-type laser can induce laser boundary image issues. Improvements in backside illuminated image sensors and/or corresponding methods for manufacturing the same are desired.

#Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIG. 1 is a flowchart of a method for making a semiconductor structure having one or more backside illuminated sensors (BSIs) constructed according to aspects of the present disclosure in one or more embodiments.

#FIGS. 2 through 5 and 11 are sectional views of the semiconductor structure having BSIs at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments.

#It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.

#FIG. 1 is a flowchart of a method 50 for making a semiconductor structure 100 having one or more backside illuminated sensors (BSIs). FIGS. 2 through 5 and 11 are sectional views of a semiconductor structure 100 at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments. FIG. 2a illustrates a sectional view of one backside illuminated sensor 104 constructed according to various aspects of the present disclosure in one embodiment. FIG. 2b illustrates a top view of one chip (die) 114 having one or more BSIs formed thereon. FIG. 6 illustrates a top view of a wafer 146 having BSIs formed thereon and a scan path of a laser annealing process applied to the backside of the wafer. FIG. 7 is a schematic view illustrating a laser beam of the laser source implemented for the laser annealing process according to one embodiment of the present disclosure. FIG. 8 illustrates a shape and dimensions of a laser beam of the laser source used for the laser annealing process constructed according to aspects of the present disclosure in another embodiment. FIG. 9 illustrates a top view of a wafer 146 having BSIs formed thereon and a plurality of fields defined thereon. FIG. 10 schematically illustrates a laser beam size of the laser source for the laser annealing process, a surface profile of the backside surface of a wafer, a pixel size of the BSIs, and imaging signals from the BSIs constructed according to aspects of the present disclosure in another embodiment. The semiconductor structure 100 and the method 50 making the same are collectively described below with reference to FIGS. 1 through 11.

#Referring to FIGS. 1 and 2, the method 50 begins at step 52 by forming, on a semiconductor substrate (or device substrate) 102, one or more backside illuminated sensors (BSIs) 104. The semiconductor substrate 102 includes silicon in a crystalline structure, such as a silicon wafer. The semiconductor substrate 102 may alternatively or additionally include other semiconductor material such as germanium, gallium arsenic, or indium phosphide. The semiconductor substrate 102 includes a front surface (or top surface) and a backside surface (or bottom surface). The semiconductor substrate 102 may include various p-type doped regions and/or n-type doped regions configured and coupled to form various devices and functional features. All doping features are formed on the front surface of the semiconductor substrate 102 and may be formed by various techniques, such as ion implantation or diffusion in various steps. The semiconductor substrate 102 may include other features such as shallow trench isolation (STI) features for isolation. For example, the STI features are formed on the front surface of the semiconductor substrate 102 and are configured to isolate various devices, such as various backside illuminated sensors 104.