Latent Space Switch using a Single Transposing Rotator

A latent space switch comprising:

• a transposing rotator having a plurality of inlets and a plurality of outlets, said transposing rotator cyclically connecting each inlet to each outlet during a rotation cycle, starting with a transposed outlet of said each inlet;
• a plurality of memory devices, each memory device alternately connecting to a respective inlet and a peer outlet of said respective inlet;
• a master controller alternately connecting to a number of inlets and peer outlets of said number of inlets;
• and
• a plurality of ports alternately connecting to:
• said plurality of inlets for transferring data to said plurality of memory devices and transferring control messages to said master controller;
• and
• said plurality of outlets for receiving data read from said plurality of memory devices and receiving downstream control messages from said master controller.

A method of switching comprising configuring a transposing rotator having N inlets and N outlets, N>2, to:

• cyclically connect each inlet to each outlet during a rotation cycle of N time slots, starting with a transposed outlet of said each inlet;
• alternately connecting, during each time slot of said rotation cycle:
• N ingress ports to said N inlets and said N outlets to N egress ports;
• and
• each memory device of a set of N memory devices to a respective inlet and a peer outlet of said respective inlet;
• receiving data at said N ingress ports, to be selectively switched to said N egress ports;
• transferring data from said N ingress ports to said N memory devices;
• and
• transferring data from said N memory devices to said N egress ports.

A method of switching comprising:

• configuring a rotator having N inlets and N outlets to cyclically connect each inlet to each outlet during a rotation cycle;
• initializing said rotator with each inlet connecting to a transposed outlet of said each inlet;
• configuring N inlet selectors and N outlet selectors to alternately connect:
• N ports to said N inlets and said N outlets to said N ports;
• each memory device of a set of M memory devices, 1<M<N, to a respective inlet and a peer outlet of said respective inlet;
• a master controller to a set of (N−M) inlets and peer outlets of said set of (N−M) inlets;
• transferring, under control of port controllers of said N ports:
• data received at said N ports from data sources to said set of M memory devices;
• control messages from said N ports to said master controller;
• and
• data from said set of M memory devices to said N ports for transmission to data sinks.