Semiconductor memory and system

A semiconductor memory comprising

• a real memory cell;
• a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal;
• a replica circuit including a plurality of replica units connected in series, each of the plurality of replica units including a plurality of dummy memory cells connected in parallel, wherein one of the plurality of dummy memory cells of one of the plurality of replica units is accessed in response to data which is read from one of the plurality of dummy memory cells of one of the plurality of replica units of a prior stage;
• and
• an operation control circuit configured to activate a dummy access signal to access one of the plurality of dummy memory cells of one of the plurality of replica units of a first stage in response to a read command, and to activate the sense amplifier enable signal in response to data read from one of the plurality of replica units of a last stage.