Non-volatile memory with both single and multiple level cells
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
Estimating the term…
Abstract
Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.
Claims20
A memory array, comprising:
- a number of single level non-volatile memory cells;
- a number of multiple level non-volatile memory cells;
- a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;
- wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells;
- wherein a second select gate is coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate;
- and
- wherein a second single level non-volatile memory cell is interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.
A memory device, comprising:
- an array of non-volatile memory cells including a string of non-volatile memory cells;
- circuitry for control and access to the array of non-volatile memory cells;
- wherein the array of non-volatile memory cells includes:
- a number of single level non-volatile memory cells;
- a number of multiple level non-volatile memory cells;
- a number of select gates coupled in series to the number of single level non-volatile memory cells and the number of multiple level non-volatile memory cells;
- wherein a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell that is directly coupled to a continuous number of additional multiple level non-volatile memory cells;
- wherein a second select gate is coupled in series to an opposite end of a number of multiple level non-volatile memory cells relative to the first select gate;
- and
- wherein a second single level non-volatile memory cell is interposed between and coupled to the second select gate and a second multiple level non-volatile memory cell, wherein the second single level non-volatile memory cell has a programmed voltage that is intermediate between a higher programmed voltage for the upper page of the second multiple level non-volatile memory cell and a lower resting voltage of the second select gate.
A method of forming a memory block, comprising:
- adding a number of word lines to a string having a number of single level non-volatile memory cells and a number of multiple level memory cells for maintaining a previous memory block size;
- wherein adding the number of word lines includes adding a number of non-volatile memory cells selected from single level non-volatile memory cells and multiple level memory cells;
- and
- wherein maintaining the previous memory block size includes maintaining a particular number selected from data input selection choices, memory bits, and pages associated with the previous memory block size.
Dependencies are inferred from the claim text.