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US 2012/0257450 A1Published application
Methods and devices for memory reads with precharged data lines
AssigneeMicron Technology, Inc.
InventorAaron Yip
Life of this patent
Estimating the term…
Abstract
Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the adjacent data line is maintained at the particular voltage. Various embodiments include the array architecture to facilitate precharging the adjacent pair of data lines to a particular voltage and maintaining the unselected data line at the particular voltage during a sensing phase of a read operation
Claims37
A memory device, comprising:
- an adjacent pair of strings of memory cells, each comprising a memory cell to store user data and two or more dummy memory cells;
- wherein a first dummy memory cell of one string of memory cells of the adjacent pair of strings of memory cells has a control gate commonly coupled to a control gate of a first dummy memory cell of the other string of memory cells of the adjacent pair of strings of memory cells;
- wherein a second dummy memory cell of the one string of memory cells has a control gate commonly coupled to a control gate of a second dummy memory cell of the other string of memory cells;
- wherein the first dummy memory cell of the one string of memory cells has a threshold voltage greater than a threshold voltage of the first dummy memory cell of the other string of memory cells;
- and
- wherein the second dummy memory cell of the one string of memory cells has a threshold voltage less than a threshold voltage of the second dummy memory cell of the other string of memory cells.
3 more elements
A memory device, comprising:
- an adjacent pair of data lines;
- an adjacent pair of strings of memory cells, each comprising a memory cell to store user data and two or more dummy memory cells;
- wherein one string of memory cells of the adjacent pair of strings of memory cells selectively provides a path from one data line of the adjacent pair of data lines to a supply node;
- wherein the other string of memory cells of the adjacent pair of strings of memory cells selectively provides a path from the other data line of the adjacent pair of data lines to the supply node;
- wherein a first dummy memory cell of the one string of memory cells has a control gate commonly coupled to a control gate of a first dummy memory cell of the other string of memory cells;
- wherein a second dummy memory cell of the one string of memory cells has a control gate commonly coupled to a control gate of a second dummy memory cell of the other string of memory cells;
- wherein the first dummy memory cell of the one string of memory cells has a threshold voltage greater than a threshold voltage of the first dummy memory cell of the other string of memory cells;
- and
- wherein the second dummy memory cell of the one string of memory cells has a threshold voltage less than a threshold voltage of the second dummy memory cell of the other string of memory cells.
6 more elements
A method of operating a memory device, comprising:
- precharging an adjacent pair of data lines to a particular voltage;
- isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage;
- and
- selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.
1 more element
A method of operating a memory device, comprising:
- precharging an adjacent pair of data lines to a particular voltage;
- isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage;
- activating two memory cells of one string of memory cells containing a memory cell selected for reading and activating only one of two memory cells of an other string of memory cells in response to first and second control signals;
- selectively activating the selected memory cell and selectively activating a memory cell of the other string of memory cells in response to a third control signal;
- activating each remaining memory cell of the one string of memory cells;
- discharging the one data line through the one string of memory cells if the selected memory cell is activated in response to the third control signal.
3 more elements
Dependencies are inferred from the claim text.