Multi-Cell Per Memory-Bit Circuit and Method
AssigneeGrandis, Inc.
InventorAdrian E. Ong
Life of this patent
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Abstract
A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.
Claims26
A memory circuit comprising:
- a write circuit adapted to provide a same bit to each of a plurality of memory cells for storage, each of the plurality of memory cells storing either the bit or a complement of the bit in response;
- and
- a read circuit adapted to receive the bits stored in the plurality of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule.
A method of operating a memory circuit, the method comprising:
- providing a same bit to each of a plurality of memory cells, each of the plurality of memory cells storing either the bit or a complement of the bit in response;
- receiving the bits stored in the plurality of memory cells;
- and
- generating an output value defined by the stored bits in accordance with a predefined rule.
Dependencies are inferred from the claim text.