Back to results
US 2012/0257441 A1Published application
Memory bit redundant vias
AssigneeTexas Instruments Incorporated
InventorsMark A. Dexter, Sarma S. Gunturi
Life of this patent
Estimating the term…
Abstract
An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.
Claims8
An integrated circuit, comprising:
- a memory bit;
- a differential sense amplifier coupled to said memory bit for reading a logic state of said memory bit;
- a bitline connected to an input of said differential sense amplifier;
- and
- a via path that couples said bitline to Vss wherein said via path contains at least one redundant via pair.
2 more elements
An integrated circuit, comprising:
- an SRAM memory bit;
- a differential sense amplifier coupled to said SRAM memory bit for reading a logic state of said SRAM memory bit;
- a bitline coupled to an input of said differential sense amplifier and also coupled to a passgate transistor of said SRAM memory bit;
- and
- a via path which couples said bitline to Vss wherein said via path contains a redundant via pair.
2 more elements
Dependencies are inferred from the claim text.