Bootstrap gate drive for full bridge neutral point clamped inverter

In a neutral-point-clamped power inverter having a positive DC bus with voltage UDC+ and a negative DC bus with voltage UDC− and a neutral bus at voltage UDC_M commonly connected to the positive and negative DC buses through capacitors C1 and C2, and having a first set (S1-S4) of serially-stacked switches between the positive and negative DC buses, where the midpoint of the first set of switches is an output of the inverter and where the neutral bus is additionally connected between a pair of diodes D1 and D2, where D1 is connected to emitter E1 of switch S1 and diode D2 is connected to emitter E3 of switch S3, the gate drive circuit comprising:

• a first gate drive block comprising a first gate drive circuit U1 and capacitors C14 and C15 connected to emitter E1 of switch S1, where C14 is also connected to U1 and indirectly to a positive signal VL1_P of a first isolated DC source through first bootstrap diode D14, and where C15 is also connected to U1 and indirectly to a first reference signal Vref1 through second bootstrap diode D15;
• a second gate drive block comprising a second gate drive circuit U2 and capacitors C16 and C17 connected to emitter E2 of switch S2, where C16 is also connected to U2 and to VL1_P, and where C17 is also connected to U2 and to a negative signal VL1_N of the first isolated DC source;
• a third gate drive block comprising a third gate drive circuit U3 and capacitors C18 and C19 connected to emitter E3 of switch S3, where C18 is also connected to U3 and indirectly to a positive signal VC_C of a second isolated DC source through third bootstrap diode D16, and where C19 is also connected to U3 and indirectly to a second reference signal Vref2 through fourth bootstrap diode D17;
• and
• a fourth gate drive block comprising a fourth gate drive circuit U4 and capacitors C20 and C21 connected to emitter E4 of switch S4, where C20 is also connected to U4 and to VC_C, and where C21 is also connected to U4 and to a negative signal VC_E of the second isolated DC source,
• where U1 selectively provides signal G1 to switch S1, U2 selectively provides signal G2 to switch S2, U3 selectively provides signal G3 to switch S3, U4 selectively provides signal G4 to switch S4,
• where signals G1-G4 are bipolar DC input signals that operate to activate or deactivate the gates of switches S1-54 in response to a control signal,
• where Vref1 and Vref2 are provide by a gate drive bias network connected across the DC bus voltage of the inverter, from UDC+ to UDC− and having a first zener diode D12 and a plurality of resistors R10-R12 that are connected in series between UDC+ and UDC_M, where R10-R12 set a bias current for diode D12, a second zener diode D13 and a plurality of resistors R20-R22 that are connected in series between UDC_M and UDC−, where R20-R22 set a bias current for diode D13, a first capacitor C12 that is connected across diode D12 and a second capacitor C13 that is connected across diode D13, where capacitors C12 and C13 function as electrolytic filter capacitors, where Vref1 is connected to C12 and D12 through a first current limiting resistor R1, and Vref2 is connected to C13 and D13 through a second current limiting resistor R2.

In a neutral-point-clamped power inverter having a positive DC bus with voltage UDC+ and a negative DC bus with voltage UDC− and a neutral bus at voltage UDC_M commonly connected to the positive DC bus through capacitors C1 and C3 and to the negative DC bus through the capacitors C2 and C4, and having a first set (S1-S4) and a second set (S5-S8) of serially-stacked switches between the positive and negative DC buses, where the midpoints of the first and second set of switches are outputs of the inverter and where the neutral bus is additionally connected between two pairs of diodes D1/D2 and D3/D4, where D1 is connected to emitter E1 of switch S1, diode D2 is connected to emitter E3 of switch S3, diode D3 is connected to emitter E5 of switch S5, diode D7 of switch S7, the gate drive circuit comprising:

• a first gate drive block comprising a first gate drive circuit U1 and capacitors C14 and C15 connected to emitter E1 of switch S1, where C14 is also connected to U1 and indirectly to a positive signal VL1_P of a first isolated DC source through first bootstrap diode D14, and where C15 is also connected to U1 and indirectly to a first reference signal Vref1 through second bootstrap diode D15;
• a second gate drive block comprising a second gate drive circuit U2 and capacitors C16 and C17 connected to emitter E2 of switch S2, where C16 is also connected to U2 and to VL1_P, and where C17 is also connected to U2 and to a negative signal VL1_N of the first isolated DC source;
• a third gate drive block comprising a third gate drive circuit U3 and capacitors C18 and C19 connected to emitter E3 of switch S3, where C18 is also connected to U3 and indirectly to a positive signal VC_C of a second isolated DC source through third bootstrap diode D16, and where C19 is also connected to U3 and indirectly to a second reference signal Vref2 through fourth bootstrap diode D17;
• and
• a fourth gate drive block comprising a fourth gate drive circuit U4 and capacitors C20 and C21 connected to emitter E4 of switch S4, where C20 is also connected to U4 and to VC_C, and where C21 is also connected to U4 and to a negative signal VC_E of the second isolated DC source,
• a fifth gate drive block comprising a fifth gate drive circuit U5 and capacitors C22 and C23 connected to emitter E5 of switch S5, where C22 is also connected to U5 and indirectly to a positive signal VL2_P of a third isolated DC source through fifth bootstrap diode D18, and where C23 is also connected to U5 and indirectly to Vref1 through sixth bootstrap diode D19;
• a sixth gate drive block comprising a sixth gate drive circuit U6 and capacitors C24 and C25 connected to emitter E6 of switch S6, where C24 is also connected to U6 and to VL2_P, and where C25 is also connected to U6 and to a negative signal VL2_N of the third isolated DC source;
• a seventh gate drive block comprising a seventh gate drive circuit U7 and capacitors C26 and C27 connected to emitter E7 of switch S7, where C26 is also connected to U7 and indirectly to VC_C through seventh bootstrap diode D20, and where C27 is also connected to U7 and indirectly to Vref2 through eight bootstrap diode D21;
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• an eighth gate drive block comprising an eighth gate drive circuit U8 and capacitors C28 and C29 connected to emitter E8 of switch S8, where C28 is also connected to U8 and to VC_C, and where C29 is also connected to U8 and to VC_E,
• where U1-U8 selectively provide signals G1-G8 to switches S1-28, respectively,
• where signals G1-G8 are bipolar DC input signals that operate to activate or deactivate the gates of switches S1-S8 in response to a control signal,
• where Vref1 and Vref2 are provide by a gate drive bias network connected across the DC bus voltage of the inverter, from UDC+ to UDC− and having a first zener diode D12 and a plurality of resistors R10-R12 that are connected in series between UDC+ and UDC_M, where R10-R12 set a bias current for diode D12, a second zener diode D13 and a plurality of resistors R20-R22 that are connected in series between UDC_M and UDC−, where R20-R22 set a bias current for diode D13, a first capacitor C12 that is connected across diode D12 and a second capacitor C13 that is connected across diode D13, where capacitors C12 and C13 function as electrolytic filter capacitors, where Vref1 is connected to C12 and D12 through a first current limiting resistor R1, and Vref2 is connected to C13 and D13 through a second current limiting resistor R2.