Multi-layered semiconductor apparatus
AssigneeNikon Corporation
InventorsISAO SUGAYA, Kazuya Okamoto
Life of this patent
Estimating the term…
Abstract
Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.
Claims51
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, wherein
- the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out.
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, comprising a control circuit that controls driving of the circuit regions such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out.
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, wherein
- at least one of the semiconductor chips includes a plurality of circuit regions that are driven during overlapping time periods, and
- the circuit regions that are driven during overlapping time periods are arranged to be separated from each other.
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, wherein
- a plurality of circuit regions that are driven during overlapping time periods contact each other within at least one of the semiconductor chips, and
- the circuit regions that are driven during overlapping time periods are arranged such that at least portions thereof are misaligned along a shared border therebetween.
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, wherein
- a first semiconductor chip, which is one of the plurality of semiconductor chips, includes a first circuit region that is driven,
- a second semiconductor chip, which is one of the plurality of semiconductor chips and is arranged to contact the first semiconductor chip, includes a second circuit region that is driven during a time period that overlaps with a time period during which the first circuit region is driven, and
- the first circuit region and the second circuit region are arranged to be separated from each other.
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, wherein
- a first semiconductor chip, which is one of the plurality of semiconductor chips, includes a first circuit region that is driven,
- a second semiconductor chip, which is one of the plurality of semiconductor chips and is arranged to contact the first semiconductor chip, includes a second circuit region that is driven during a time period that overlaps with a time period during which the first circuit region is driven, and
- the first circuit region and the second circuit region are arranged such that at least portions thereof are misaligned along a shared border therebetween.
A multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, wherein
- a first semiconductor chip, which is one of the plurality of semiconductor chips, includes a first circuit region that is driven,
- a second semiconductor chip, which is one of the plurality of semiconductor chips, includes a second circuit region that overlaps with the first circuit region in a direction of the chip layering and that is driven during a time period that overlaps with a time period during which the first circuit region is driven, and
- the multi-layered semiconductor apparatus comprises a non-heat-generating region arranged between the first circuit region and the second circuit region.
A control method of a multi-layered semiconductor apparatus including a plurality of layered semiconductor chips that each include at least one circuit region, comprising
- controlling driving of the circuit regions such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out.
Dependencies are inferred from the claim text.