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US 2012/0256309 A1Published application
Integrated Circuit Having Pitch Reduced Patterns Relative To Photolithography Features
AssigneeRound Rock Research, LLC
InventorsLuan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Abstract
An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
Claims18
A partially formed integrated circuit, comprising:
- a substrate;
- a primary mask layer overlying the substrate, the primary mask layer formed of a material different from photoresist;
- a patterned lower hard mask layer overlying the primary mask layer;
- a patterned upper hard mask layer overlying the lower mask layer;
- and
- a plurality of spacers defining a first pattern in a first plane overlying the upper hard mask layer,
- wherein a part of the upper hard mask layer has an exposed top surface and defines a second pattern over the lower hard mask layer.
4 more elements
Dependencies are inferred from the claim text.