Self-aligned nano-structures
AssigneeMicron Technology, Inc.
InventorGurtej Sandhu
Life of this patent
Estimating the term…
Abstract
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.
Claims20
A semiconductor assembly comprising:
- an aperture formed in a dielectric layer;
- and
- an additional structure formed in the center and below the aperture, wherein the structure is narrower than the width of the second aperture and wherein the structure has a width of approximately 45 nm or less.
The semiconductor assembly of claim 11, wherein the structure has a width of approximately 35 nm or less.
A semiconductor assembly comprising:
- a first trench formed through an insulative layer, wherein the first trench has a first width;
- a second trench formed through the insulative layer, parallel to the first trench, wherein the second trench has a second width greater than the first width;
- a polymer layer formed on the insulative layer and in each of the first trench and the second trench, such that the first trench is completely filled with the polymer layer and the second trench is partially filled with the polymer layer;
- and
- a contact via within the second trench.
A semiconductor assembly, comprising:
- an insulative layer;
- a trench formed in the insulative layer, wherein the trench comprises a region having a width that is wider than a width of the trench on either side of the region;
- spacers formed on sidewalls of the trench and sidewalls of the region;
- and
- a contact via formed through the insulative layer at a base of the region.
A semiconductor assembly, comprising:
- a dielectric material having a first trench and a second trench formed therein;
- polymer spacers formed on sidewalls of the first trench;
- and
- a contact via formed in the dielectric material between the sidewall spacers and at an intersection of the first trench and the second trench.
A semiconductor assembly, comprising:
- an insulative layer having a first trench formed therethrough;
- a polymer layer formed within the first trench to form spacers on sidewalls of the first trench;
- and
- a contact via formed at a base of the first trench, between the sidewall spacers.
A semiconductor assembly, comprising:
- a dielectric layer;
- a first aperture formed in the dielectric layer and having a first width;
- a second aperture formed in the dielectric layer and having a second width, wherein the first width and the second width are approximately the same and wherein the first aperture and the second aperture intersect;
- a polymer formed in the first and second apertures;
- and
- an additional structure formed at an intersection of the first aperture and the second aperture.
Dependencies are inferred from the claim text.