Method and Apparatus for Modeling Multi-terminal MOS Device for LVS and PDK

A semiconductor structure comprising:

• a p-type substrate;
• a first deep n-type well region, a first n-type well region formed on the p-type substrate;
• a first p-type well formed within a first isolation tub formed by the first deep n-type well region and the first n-type well region;
• a first drain region, a first source region and a first body contact region formed in the first p-type well;
• a first gate electrode formed over the first P-type well;
• a second deep n-type well region, a second n-type well region formed on the p-type substrate;
• a second p-type well formed within a second isolation tub formed by the second deep n-type well region and the second n-type well region;
• a second drain region, a second source region and a second body contact region formed in the second p-type well;
• a second gate electrode formed over the second P-type well;
• and
• a dummy device connected between the first body contact region and the second body contact region.

A method for reviewing a layout comprising:

• identifying a semiconductor device layout region comprising:
• a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes;
• and
• adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.