Semiconductor devices including dual gate structures and methods of fabrication

A method of forming a dual gate structure, the method comprising:

• forming a conductive nitride material on an n-type field effect transistor (nFET) device region and a p-type field effect transistor (pFET) device region of a semiconductor substrate;
• converting to an oxide material a portion of the conductive nitride material disposed over the nFET device region to form an oxide material region over the nFET device region without converting to the oxide material another portion of the conductive nitride material disposed over the pFET device region;
• and
• forming another conductive material on the oxide material region and the another portion of the conductive nitride material, the another conductive material having a work function differing from a work function of the conductive nitride material.

A method of forming a dual gate structure, the method comprising:

• forming an isolating structure supported by a semiconductor substrate and isolating an n-type field effect transistor (nFET) device region from a p-type field effect transistor (pFET) device region;
• forming a dielectric material on the isolating structure;
• forming a conductive material on the dielectric material;
• exposing a region of the conductive material overlying the isolating structure to an oxidizing environment while not exposing another region of the conductive material overlying the isolating structure to the oxidizing environment to form a region of a converted dielectric material adjacent to the another region of the conductive material;
• forming another conductive material on the region of the converted dielectric material and the another region of the conductive material;
• and
• exposing at least a portion of the isolating structure laterally disposed between at least a portion of the region of the converted dielectric material and at least a portion of the another region of the conductive material.

A semiconductor device, comprising:

• a dual gate structure, comprising:
• a semiconductor substrate comprising:
• an n-type field effect transistor (nFET) device region;
• and
• a p-type field effect transistor (pFET) device region;
• a gate structure comprising:
• a dielectric region on the pFET device region, the dielectric region comprising a high-K dielectric material;
• a high work function region on the dielectric region comprising a conductive material;
• and
• a low work function region on the high work function region comprising another conductive material;
• and
• another gate structure comprising:
• another dielectric region on the nFET device region, the another dielectric region comprising the high-K dielectric material;
• a converted dielectric region on the another dielectric region comprising an oxide of the conductive material;
• and
• another low work function region on the converted dielectric region comprising the another conductive material.