Integrated circuit structure having substantially planar n-p step height and methods of forming
AssigneesGlobalfoundries Inc., International Business Machines Corporation
InventorsWeipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
Life of this patent
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Abstract
Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
Claims17
A method comprising:
- providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region;
- forming a mask over the PFET region to leave the NFET region exposed;
- performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region;
- and
- forming a silicon germanium (SiGe) channel in the PFET region after the performing of the DHF.
A method of forming an integrated circuit structure having a substantially planar shallow trench isolation (STI) profile across an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region, the method comprising:
- providing a structure having the NFET region and the PFET region;
- forming a mask over the PFET region to leave the NFET region exposed;
- and
- performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region,
- wherein the substantially lower STI profile allows for planarizing of the STI profile of the NFET region and an STI profile of the PFET region after subsequent formation of a silicon germanium (SiGe) portion of the PFET region.
An integrated circuit structure comprising:
- an n-type field effect transistor (NFET) region having a first shallow trench isolation (STI) step height;
- and
- a p-type silicon germanium field effect transistor (SiGe PFET) region having a second STI step height;
- wherein the first STI step height is located at approximately a same device depth as the second STI step height.
Dependencies are inferred from the claim text.