Trench power mosfet structure with high cell density and fabrication method thereof

A fabrication method of a trench power MOSFET structure with high cell density comprising the steps of:

• forming at least a gate trench in a silicon substrate;
• forming a gate dielectric layer lining exposed surfaces of the silicon substrate;
• forming a gate polysilicon structure in the gate trench;
• forming a passivation layer in the gate trench to cover the gate polysilicon structure;
• forming a body region having a first conductive type in the silicon substrate;
• forming a source doped region by implanting impurities of a second conductive type into the body region;
• removing a portion of the gate dielectric layer and the passivation layer so as to expose the gate polysilicon structure and the source doped region;
• forming a dielectric spacer with a predetermined thickness on a sidewall of the gate trench;
• depositing a metal layer on the exposed surfaces of the gate polysilicon structure and the source doped region;
• forming a first self-aligned silicide layer on the gate polysilicon structure and a second self-aligned silicide layer on the source doped region by using a thermal process;
• forming a dielectric structure in the gate trench to shield the first self-aligned silicide layer;
• and
• forming a source metal layer on the dielectric structure and the second self-aligned silicide layer.