Structure and fabrication process of super junction mosfet

A super junction metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:

• a drain;
• a second conductive substrate above the drain;
• a source area above the second conductive substrate, from bottom to top, the sources including a first conductive drift area, a first conductive emitting area above one side of the first conductive drift area, and the second conductive area between the first conductive emitting area and the first conductive drift area;
• a side-wall isolation structure being above the second conductive substrate and contacting with one side of the source area that is close to the first conductive source area, height of such isolation structure being lower than thickness of said source area such that the side-wall of the first conductive emitting area and the second conductive body being not blocked by the side-wall isolation structure;
• a gate being above the second conductive body area of the source area;
• a surface isolation structure being above the gate and covering upper surfaces of the first conductive source area and the first conductive drift area;
• a source electrode covering the side-wall surface isolation structure and it extending downward from one side of the source area that is close to the first conductive emitting area to reach in the side-wall isolation structure, and being conductive with the first conductive emitting area and the second conductive body area.

A fabrication process of super junction MOSFET comprising the following steps:

• i) forming an epitaxial layer (EPI) above a semiconductor substrate and forming a gate area on the epitaxial layer;
• ii) forming a surface isolation area around the gate area to cover both the gate area and partial upper surface of periphery of the gate area;
• iii) forming a heavily doped first and second conductive areas inside the EPI on one side of the surface isolation area such that both the first and second conductive areas extend below the said surface isolation area and the second conductive area isolates the first conductive area from the rest of the EPI;
• iv) using self aligned technology to etch along the surface isolation structure downward to etch off a part of the first conductive area and a part of the second conductive area which are not covered by the surface isolation structure, and forming a trench in the epitaxial layer;
• v) applying heat treatment diffusion method to enlarge the first and second conductive areas such that the second conductive area is extended below the gate;
• vi) filling dielectric materials in the trench, and using etch-back techniques to erase the excessive dielectric material to expose the side-wall of both the first and second conductive areas, remaining dielectric in the trench forms the side-wall isolation structure;
• vii) making an upper electrode to make it cover the surface of the surface isolation structure, extend into the side wall isolation structure from the trench downward, and contact the side walls of the first and second conducive areas;
• and
• viii) making the lower electrode underneath the semiconductor substrate.

A fabrication process of super junction MOSFET comprising the following steps:

• i) forming a first conductive epitaxial layer on a semiconductor substrate and forming a gate area on the epitaxial layer;
• ii) forming a surface isolation structure around the gate area to cover both the gate area and a part of upper surface of the epitaxial around the gate area;
• iii) forming of heavily doped first and second conductive areas inside the epitaxial layer on one side of the surface isolation area such that both the first and second conductive areas extend below the surface isolation structure, the second conductive area being the first conductive area and separating the first conductive area with the rest of the epitaxial layer;
• iv) using self aligned technology to etch along the surface isolation structure downward to etch off a part of the first conductive area and a part of the second conductive area which are not covered by the surface isolation structure, and forming a trench in the epitaxial layer;
• v) applying the tilt ion implantation method to form a second conductive lightly doped buffer layer underneath the second conductive area from the side wall of the trench;
• vi) applying heat treatment diffusion method to enlarge the first and second conductive areas such that the second conductive area is extended below the gate
• vii) using self alignment technology to etch off the excessive heavily doped second conductive material formed at the bottom of the trench due to the tilt ion implantation specified in step v) along the edge of the surface isolation structure downward;
• viii) filling the trench with dielectric material and removing the extra dielectric material on upper part of the trench through etchback technique to expose the side-wall of the first and second conductive areas, the remaining dielectric material forming the side-wall isolation structure;
• ix) making an upper electrode to make it cover the surface of the surface isolation structure, extend into the side wall isolation structure from the trench downward, and contact the side walls of the first and second conducive areas;
• and
• x) making a lower electrode underneath the semiconductor substrate.