Semiconductor device
AssigneeSeiko Instruments Inc.
InventorYuichiro Kitajima
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Abstract
An ESD protection element is disclosed in which LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to maintain an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again.
Claims8
A semiconductor device, comprising:
- a gate insulating film formed on a surface of a p-type semiconductor region;
- a gate electrode disposed on the gate insulating film;
- LOCOS oxide films disposed on portions of the surface of the p-type semiconductor region, the portions being located at both ends of the gate electrode;
- a p-type channel stop diffusion layer disposed below one of the LOCOS oxide films;
- a p-type high concentration diffusion layer disposed on the p-type semiconductor region so as to contact the p-type channel stop diffusion layer;
- a first n-type high concentration diffusion layer disposed on the p-type semiconductor region so as to contact the p-type high concentration diffusion layer, wherein the first n-type high concentration diffusion layer is surrounded by the p-type high concentration diffusion layer in a planar manner;
- an n-type channel stop diffusion layer disposed below another one of the LOCOS oxide films;
- and
- a second n-type high concentration diffusion layer disposed to be in contact with the n-type channel stop diffusion layer.
The semiconductor device according to claim 1, wherein:
- the p-type high concentration diffusion layer, the first n-type high concentration diffusion layer, and the gate electrode, which are electrically connected to one another according to claim 5, are connected to a potential Vss;
- and
- the second n-type high concentration diffusion layer is connected to a power supply terminal Vdd.
The semiconductor device according to claim 1, wherein:
- the p-type high concentration diffusion layer, the first n-type high concentration diffusion layer, and the gate electrode, which are electrically connected to one another according to claim 5, are connected to a potential Vss;
- and
- the second n-type high concentration diffusion layer is connected to an input/output terminal.
Dependencies are inferred from the claim text.