Semiconductor device for reducing interconnect pitch

A semiconductor device, comprising a logic circuit including a plurality of transistors, wherein

• the logic circuit includes:
• a bottom electrode which is one electrode from among three electrodes of source, drain, and gate electrodes of the plurality of transistors which include a channel region so that a channel width direction thereof is a first direction and a channel longitudinal direction thereof is a second direction;
• a plurality of first wirings which are connected to a plurality of local wirings formed above the plurality of gate electrodes and to the plurality of bottom electrodes corresponding to the plurality of local wirings, the plurality first wirings are formed above the plurality of local wirings, and are connected to the plurality of local wirings corresponding to the plurality of local wirings;
• and
• a plurality of second wirings formed above the plurality of first wirings and connected to the plurality of first wirings corresponding to the plurality of first wirings, wherein
• the plurality of local wirings and the plurality of first wirings are disposed substantially parallel to the first direction,
• each pattern end of the plurality of first wirings are disposed substantially in line in the second direction, places that connects each of the plurality of first wirings to each of the plurality of corresponding local wirings are disposed substantially in line in the second direction, and
• the plurality of second wirings are disposed substantially parallel to the second direction.

A wiring layout method for drawing out any one electrode from among three electrodes of source, drain, and gate electrodes of a plurality of transistors in a semiconductor device having the plurality of transistors, the method comprising:

• arranging the any one electrode from among the three electrodes in a rectangular region so that a direction of a long side in the rectangular region is a first direction and a direction of a short side is a second direction;
• arranging a plurality of the any one electrode from among the three electrodes in parallel in the second direction;
• arranging a plurality of local wirings arranged above the plurality of gate electrodes and connected to the plurality of the any one electrode from among the three electrodes so as to be in parallel in the second direction;
• arranging a plurality of first wirings formed above the plurality of local wirings to have the same length in the second direction;
• connecting each of the plurality of first wirings to each of the plurality of corresponding local wirings in line in the second direction;
• and
• arranging a plurality of second wirings formed above the plurality of first wirings and connected to the plurality of corresponding first wirings to be in parallel in the first direction so that a longitudinal direction of each of the plurality of second wirings extends in the second direction.