Method for increasing penetration depth of drain and source implantation species for a given gate height
AssigneeAdvanced Micro Devices, Inc.
InventorsUWE GRIEBENOW, KAI FROHBERG, FRANK FEUSTEL, THOMAS WERNER
Life of this patent
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Abstract
The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.
Claims16
1-11. (canceled)
A method, comprising:
- forming a drain mask above a drain region of a transistor so as to cover said drain region and expose a source region;
- performing a source implantation process to implant a dopant species into said source region of said transistor by using said drain mask and a gate electrode as an implantation mask, said source implantation process comprising at least one implantation step using a tilt angle;
- forming a source mask above said source region to cover said source region and expose said drain region;
- and
- performing a drain implantation process to implant said dopant species into said drain region by using said source mask and said gate electrode as an implantation mask, said drain implantation process comprising at least one implantation step using a tilt angle.
A method, comprising:
- forming drain and source extension regions in a semiconductor layer adjacent to a gate electrode structure of a P-channel transistor;
- increasing the shielding effect of said gate electrode with respect to an implantation process for forming deep drain and source regions of said P-channel transistor;
- and
- introducing a P-type dopant into said semiconductor layer using said gate electrode as an implantation mask for substantially avoiding penetration of said P-type dopant into a channel region of said transistor.
A semiconductor device formed by a process comprising:
- forming a drain mask above a drain region of a transistor so as to cover said drain region and expose a source region;
- performing a source implantation process to implant a dopant species into said source region of said transistor by using said drain mask and a gate electrode as an implantation mask, said source implantation process comprising at least one implantation step using a tilt angle;
- forming a source mask above said source region to cover said source region and expose said drain region;
- and
- performing a drain implantation process to implant said dopant species into said drain region by using said source mask and said gate electrode as an implantation mask, said drain implantation process comprising at least one implantation step using a tilt angle.
Dependencies are inferred from the claim text.