Layout scheme and method for forming device cells in semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
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Abstract
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
Claims20
A method for forming a semiconductor device comprising:
- forming a substructure including device cells and a pair of transistors spaced apart from one another and having respective gates, said device cells including at least three metal-metal interconnect layers including a lower metal-metal interconnect layer, a middle metal-metal interconnect layer and an upper metal-metal interconnect layer;
- forming a pattern in said middle metal-metal interconnect layer using only one photomask and only one etching operation;
- and
- forming a first metal pattern in said lower metal-metal interconnect layer, said first metal pattern comprising a first metal lead that couples said gates of said pair of transistors.
A method for forming a word line decoder semiconductor device comprising:
- forming a substructure including word line decoder cells and a pair of transistors spaced apart from one another and having respective gates coupled by a polysilicon lead, said word line decoder cells including three metal interconnect layers including a lower metal interconnect layer, a middle metal interconnect layer and an upper metal interconnect layer;
- forming a second metal pattern in said second metal interconnect layer using only one photomask, only one photolithography exposure operation and only one etching operation;
- and
- coupling said pair of transistors together using a metal lead from said second metal pattern, said metal lead extending through said word line decoder cell.
A semiconductor word line decoder device comprising:
- a plurality of word line decoder device cells including multiple patterned metal-metal interconnect layers including at least a lower patterned metal-metal interconnect layer, a middle patterned metal-metal interconnect layer and an upper patterned metal-metal interconnect layer;
- and
- a pair of transistors spaced apart from one another and having respective gates coupled by a polysilicon lead and further coupled by a metal lead of one of said lower patterned metal-metal interconnect layer and said middle patterned metal-metal interconnect layer.
Dependencies are inferred from the claim text.