Electrostatic discharge shunting circuit
AssigneeUniversity of Central Florida Research Foundation, Inc.
InventorsQIANG CUI, JUIN JEI LIOU
Life of this patent
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Abstract
An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer.
Claims20
An electrostatic discharge (ESD) shunting circuit, comprising:
- a III-V semiconductor layer, and
- a first drain-less high electron mobility transistor (HEMT) or metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or a MESFET having a second gate formed in said substrate, said HEMTs or MESFETs including:
- a donor layer on said semiconductor layer;
- no drains, and
- a source including a ohmic contact layer on said donor layer.
An electrostatic discharge (ESD) protection circuit, comprising:
- a III-V semiconductor layer;
- an ESD trigger circuit for coupling between a first terminal to be protected and a second terminal;
- and
- an ESD shunting circuit including a first drain-less high electron mobility transistors (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in said substrate, at least one source, a donor layer on said semiconductor layer, no drains, wherein said first gate is coupled to receive a triggering signal from said ESD trigger circuit and said second gate is configured for coupling to said first terminal,
- wherein said ESD shunting circuit provides a conducting channel between said second gate and said source during an ESD event at said first terminal.
An integrated circuit (IC), comprising:
- a III-V semiconductor layer;
- functional circuitry on said semiconductor layer configured to realize and carry out a functionality having a plurality of terminals including a first terminal and a ground terminal;
- an electrostatic discharge (ESD) protection circuit on said semiconductor layer, including:
- an ESD trigger circuit connected to said first terminal;
- and
- an ESD shunting circuit including a first drain-less high electron mobility transistors (HEMT) or metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate, at least one source connected to said ground terminal, no drains or floating drains, wherein said first gate is coupled to receive a triggering signal upon an ESD event from said ESD trigger circuit, and wherein said second gate is coupled to said first terminal,
- wherein said (ESD) shunting circuit provides a conducting channel between said second gate and said source during said ESD event.
Dependencies are inferred from the claim text.