Monolithic integrated capacitors for high-efficiency power converters

A semiconductor structure, comprising:

• a power die comprising:
• a semiconductor substrate;
• a high-side output power device over the semiconductor substrate at a first location;
• a low-side output power device over the semiconductor substrate at a second location laterally adjacent to the first location;
• a dielectric layer over the high-side output power device and the low-side output power device;
• a first metal layer over the dielectric layer and a portion of the low-side output power device;
• and
• an integrated capacitor in the power die, the integrated capacitor comprising:
• a first electrode layer within the dielectric layer;
• a second electrode layer including the first metal layer;
• and
• a portion of the dielectric layer that is between the first electrode layer and the second electrode layer.

A packaged power converter device, comprising:

• a conductive substrate;
• a power die having an upper surface and a lower surface, the upper surface including a monolithic integrated capacitor and the lower surface mounted to the conductive substrate, the power die including a voltage-in layer coupled to a drain of a device in the power die and a ground layer coupled to a source of a device in the power die;
• and
• a packaging material encapsulating the power die and at least a portion of the conductive substrate.

An electronic system comprising:

• at least one processor:
• at least on memory unit operatively coupled to the processor;
• and
• at least one power converter electrically coupled to the processor and the memory unit, the power converter comprising:
• a conductive substrate;
• a power die having an upper surface and a lower surface, the upper surface including a monolithic integrated capacitor and the lower surface mounted to the conductive substrate, the power die including a voltage-in layer coupled to a drain of the power die and a ground layer coupled to a source of the power die;
• and
• a packaging material encapsulating the power die and at least a portion of the conductive substrate;

A method of manufacturing a semiconductor device with an integrated capacitor, the method comprising:

• providing a semiconductor substrate comprising a high-side device at a first location, and a low-side device at a second location;
• forming a first metal layer over the high-side device;
• electrically coupling the first metal layer to the high-side device;
• forming a second metal layer over the low-side device;
• electrically coupling the second metal layer to the low-side device;
• forming a dielectric layer over a portion of the first metal layer and a portion of the second metal layer, the portions of the first and second metal layers configured to respectively operate as a first bottom electrode and a second bottom electrode of the integrated capacitor;
• forming a top metal layer over the dielectric layer such that the top metal layer is configured to operate as a top electrode of the integrated capacitor.

A method of manufacturing a semiconductor device with an integrated capacitor, the method comprising:

• providing a semiconductor substrate comprising a high-side device at a first location, and a low-side device at a second location;
• forming a dielectric layer over the high-side device and the low-side device;
• forming a metal layer over the dielectric layer and a portion of the low-side device;
• and
• forming a first electrode layer within the dielectric layer and over the portion of the low-side device such that the integrated capacitor comprises:
• the first electrode layer within the dielectric layer;
• a second electrode layer that includes the metal layer;
• and
• a portion of the dielectric layer that is between the first electrode layer and the second electrode layer.