Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsRiichiro TAKEMURA, Kenzo KUROTSUCHI, Takayuki KAWAHARA
Life of this patent
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Abstract
For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
Claims12
A semiconductor device comprising:
- a first transistor including a first impurity region formed in the semiconductor substrate and a second impurity region formed in the semiconductor substrate;
- a second transistor including the first impurity region and a third impurity region formed in the semiconductor substrate;
- a first chalcogenide film formed over the first transistor and second transistor, the first chalcogenide film retaining data based on electric resistance;
- a first wiring formed over the first transistor and second transistor;
- and
- a second wiring formed over the first transistor and second transistor,
- wherein the first transistor and the second transistor share the first impurity region,
- wherein a bottom surface of the first chalcogenide film is electrically connected to the first impurity region,
- wherein a top surface of the first chalcogenide film is electrically connected to the first wiring, and
- wherein the second impurity region and the third impurity region are electrically connected to the second wiring.
A semiconductor device comprising:
- a first transistor including a first impurity region formed in the semiconductor substrate and a second impurity region formed in the semiconductor substrate;
- a second transistor including the first impurity region and a third impurity region formed in the semiconductor substrate;
- a first chalcogenide film formed over the first transistor and second transistor;
- a first wiring formed over the first chalcogenide film and extending to a first direction;
- and
- a second wiring formed over the first wiring and extending to a second direction perpendicular to the first direction,
- wherein the first transistor and second transistor are disposed in the second direction,
- wherein the first transistor and the second transistor share the first impurity region,
- wherein a bottom surface of the first chalcogenide film is electrically connected to the first impurity region,
- wherein a top surface of the first chalcogenide film is electrically connected to the first wiring, and
- wherein the second impurity region and the third impurity region are electrically connected to the second wiring.
Dependencies are inferred from the claim text.