Memory device and method of manufacturing the same
AssigneePanasonic Corporation
InventorsKoji Arita, Takumi Mikawa
Life of this patent
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Abstract
Disclosed is a memory device provided with a plurality of memory cells and a lead-out line (12) shared among the memory cells. Each memory cell is provided with a transistor (6) formed above a substrate (1) and a variable resistance element (10) having a lower electrode (7), an upper electrode (9) that comprises a noble metal, and a variable resistance layer (8) disposed between the lower electrode (7) and the upper electrode (9). The resistance value of the variable resistance layer (8) changes reversibly in response to electric pulses that go through the transistor (6) and are applied between the lower electrode (7) and the upper electrode (9). The lead-out line (12) is in direct contact with the upper electrodes (9) of the memory cells.
Claims9
A memory device comprising:
- a plurality of memory cells;
- and
- a lead-out line provided in common to said plurality of memory cells,
- wherein each of said memory cells includes:
- a transistor formed above a substrate;
- and
- a variable resistance element which includes a lower electrode, an upper electrode comprising a noble metal, and a variable resistance layer disposed between said lower electrode and said upper electrode,
- said variable resistance layer has a resistance value that changes reversibly in response to an electric pulse that goes through said transistor and is applied between said lower electrode and said upper electrode,
- said lead-out line is in direct contact with said upper electrode included in each of said memory cells, and the bottommost surface of the bottom surface of said lead-out line is formed to be lower than the top surface of said upper electrode and higher than the top surface of said lower electrode, and
- said upper electrode is completely covered by said lead-out line.
A method of manufacturing a memory device including a plurality of memory cells each of which includes a transistor and a variable resistance element, the method comprising:
- forming the transistor above a substrate;
- forming a lower electrode of the variable resistance element to correspond to the transistor;
- forming a variable resistance layer on the lower electrode;
- forming an upper electrode comprising a noble metal on the variable resistance layer;
- forming an interlayer insulating layer so as to cover the variable resistance element;
- exposing at least a portion of a top surface of the upper electrode;
- and
- forming a lead-out line that is provided in common to the plurality of memory cells so as to be in direct contact with the upper electrode and such that the bottommost surface of the bottom surface of the lead-out line is lower than the top surface of the upper electrode and higher than the top surface of the lower electrode,
- the lead-out line being formed such that the upper electrode is completely covered by the lead-out line.
Dependencies are inferred from the claim text.