US 2012/0256151 A1 · Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays

Abstract

Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

Claims47

Dependent claims

A memory cell comprising programmable material directly between a pair of electrodes, and configured to have a switching volume that does not directly contact either of the electrodes;

wherein the programmable material comprises a pair of programmable material plates which are adjacent one another along edges of the plates, and wherein the switching volume is along an interface of the adjacent edges.

A memory cell, comprising:

a bottom electrode;
at least three programmable material plates over the bottom electrode;
the programmable material plates defining at least two switching volumes;
a first switching volume being configured to switch from an “A” memory state to a “B” memory state under first programming conditions, and being configured to switch from the “B” memory state to the “A” memory state under second programming conditions;
a second switching volume being configured to switch from a “C” memory state to a “D” memory state under third programming conditions, and being configured to switch from the “D” memory state to the “C” memory state under fourth programming conditions;
the first, second, third and fourth programming conditions all differing from one another so that the memory cell has four selectable memory states;
and
a top electrode over the programmable material plates.

5 more elements

A memory cell, comprising:

a bottom electrode;
at least three programmable material plates over the bottom electrode;
the programmable material plates defining at least two switching volumes;
a first switching volume being configured to switch relatively rapidly between “A” and “B” memory states, and a second switching volume being configured to switch relatively slowly between “C” and “D” memory states;
and
a top electrode over the programmable material plates.

3 more elements

A method of forming an array of memory cells, comprising:

providing an array of bottom electrodes across a supporting base, the array comprising rows and columns;
the rows extending primarily along a first axis, and the columns extending primarily along a second axis that intersects the first axis;
forming first blocks that extend primarily along the first axis;
the first blocks extending across alternating spaces between adjacent rows of the bottom electrodes and partially covering the bottom electrodes, the first blocks having edges extending upwardly from upper surfaces of the bottom electrodes;
patterning first programmable material lines along the sidewalls of the first blocks;
forming second blocks that extend primarily along the second axis;
the second blocks extending across alternating spaces between adjacent columns of the bottom electrodes and partially covering the bottom electrodes, the second blocks having edges directly over upper surfaces of the bottom electrodes;
patterning second programmable material lines along the sidewalls of the second blocks;
forming top electrode material over the second programmable material lines;
forming masking material lines over the top electrode material, and over the second programmable material lines;
and
transferring a pattern from the masking material, through the top electrode material, and through the first programmable material lines with one or more etches.

9 more elements

A method of forming an array of memory cells, comprising:

providing an array of bottom electrodes across a supporting base, the array comprising rows and columns;
the rows extending primarily along a first axis, and the columns extending primarily along a second axis that intersects the first axis;
dielectric material being between adjacent bottom electrodes of the array, the bottom electrodes being exposed at bottoms of openings that extend through the dielectric material;
forming spacers within the openings to narrow the openings;
the narrowed openings being slots that extend primarily along the first axis;
forming first programmable material within the slots to form a plurality of first programmable material plates supported edgewise over the bottom electrodes;
forming second programmable material lines over the first programmable material plates;
the second programmable material lines extending primarily along the second axis;
individual second programmable material lines being directly against multiple first programmable material plates;
and
forming top electrode material lines over and directly against the second programmable material lines.

8 more elements

Dependencies are inferred from the claim text.

Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays

Life of this patent

Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays

Life of this patent

Abstract

Claims47